S3050

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

July 9, 1999 / Revision D

BiCMOS PECL CLOCK GENERATOR

DEVICE
SPECIFICATION

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

S3050

FEATURES

Micro-power Bipolar technology

Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation

On-chip high frequency PLL with internal
loop filter for clock recovery

Supports clock recovery for:
OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps) NRZ data

155.52 MHz reference frequency

Lock detect--monitors frequency

Low-jitter serial interface

+5V supply

32 TQFP/TEP package

GENERAL DESCRIPTION

The function of the S3050 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3050 is implemented using
AMCC's proven Phase Locked Loop (PLL) technology.

The S3050 receives an OC-48, OC-24, GBE, OC-
12, or OC-3 scrambled NRZ signal and recovers
the clock from the data. The chip outputs a differ-
ential bit clock and retimed data. Figure 1 shows a
typical network application.

The S3050 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a voltage
controlled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A func-
tional block diagram is shown in Figure 2.

Figure 1. System Block Diagram

Network Interface

Processor

S3045

S3041

S3042

S3041

OTX

ORX

OTX

ORX

Network Interface

Processor

S3045

S3050

This product is not released
and the specifications herein
are subject to change.

S3050

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

July 9, 1999 / Revision D

S3050 FUNCTIONAL DESCRIPTION

The S3050 clock recovery device performs the clock
recovery function for SONET OC-48, OC-24, Gigabit
Ethernet, OC-12, or OC-3 serial data links. The chip
extracts the clock from the serial data inputs and
provides retimed clock and data outputs. A 155.52
MHz (156.25 for Gigabit Ethernet) reference clock is
required for phase locked loop start up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate. The
input data rate is selected by the RATESEL[1:0]
inputs. (See Table 1.)

Clock Recovery

Clock Recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.

The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.

Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLKP/N)
that the PLL locks onto when data is lost. If the Fre-
quency of the incoming signal is not within the range
stated in Table 4 with respect to REFCLKP/N, the PLL
will be declared out of lock, and the PLL will lock to the
reference clock. The assertion of Signal Detect (SDN)
will also cause an out of lock condition.

0
0
1
1

0
1
0
1

Table 1. Data Rate Select

The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields a typical
capture time as stated in Table 4 for random incom-
ing NRZ data.

The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.

Lock Detect

The S3050 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the value
stated in Table 4, the PLL will be declared out of lock.
The lock detect circuit will poll the input data stream in
an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the specifi-
cation as in Table 4, the PLL will be declared in lock
and the lock detect output will go active.

S3050

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

July 9, 1999 / Revision D

Figure 3. Input Jitter Tolerance Specification

Figure 4. Jitter Transfer Specification

1. Bellcore Specifications: GR-253- CORE, Issue 2,

December 1995.

2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.

0.15

1.5

Sinusodal

Input Jitter

Amplitude

(UI p-p)

Frequency

Jitter

Transfer

Frequency

Acceptable

Range

slope = -20 dB/decade

CHARACTERISTICS

Performance

The S3050 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.

Input Jitter Tolerance

Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.

)

(

)

(

)

(

)

(

)

(

)

(

)

(

1. Not specified in GR-253 and G.958.

Jitter Transfer

Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.

Jitter Generation

The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 4).

S3050

MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT

July 9, 1999 / Revision D

5
6

)

(

8
9

]

[

)

(

)

(

)

(

)

(

)

(

Table 2. Pin Assignment and Descriptions

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3049

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3049