1
S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
December 6, 1999 / Revision NC
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3064
FEATURES
Micro-power Bipolar technology
Complies with Bellcore and ITU-T
specifications
Supports 2.488 Gbps (OC-48)
Interface to both LVPECL and TTL logic
16-bit Differential LVPECL data path
Compact 100 TQFP/TEP package
Diagnostic loopback mode
Line loopback
Signal detect input
Low jitter LVPECL interface
Single 3.3V supply
Typical Power 990 mW
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
S3064
GENERAL DESCRIPTION
The S3064 SONET/SDH DeMUX chip is a fully inte-
grated deserialization SONET OC-48 (2.488 Gbps)
interface device. The chip performs all necessary se-
rial-to-parallel and framing functions in conformance
with SONET/SDH transmission standards. The de-
vice is suitable for SONET-based ATM applications.
Figure 1 shows a typical network application.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3064 is pack-
aged in a 100 TQFP/TEP, offering designers a small
package outline.
Network Interface
Processor
Network Interface
Processor
S3063
Tx
S3064
Rx
S3064
Rx
S3063
Tx
OTX
ORX
OTX
ORX
16
16
16
16
S3056
S3056
S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
2
December 6, 1999 / Revision NC
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each of
the layers has overhead bandwidth dedicated to ad-
ministration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream car-
rying voice, data, and video signals. Its main functions
are synchronization, multiplexing, and reliable trans-
port. The path layer is responsible for the actual trans-
port of services at the appropriate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-
N signal is
made up of
N byte-interleaved STS-1 signals. The
optical counterpart of each STS-
N signal is an opti-
cal carrier level-
N signal (OC-N). The S3064 chip
supports the OC-48 data rate (2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48
consists of 144 transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This
pattern of 144 overhead and 4176 SPE bytes is re-
peated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Table 1. SONET Signal Hierarchy
Figure 2. SONET Structure
Figure 3. STS-48/OC-48 Frame Format
9 Rows
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
sec
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End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
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transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Functions
3
S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
December 6, 1999 / Revision NC
The sequence of operations of the S3064 is as follows:
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 9. Internal clocking and control
functions are transparent to the user.
S3064 OVERVIEW
The S3064 receiver implements SONET/SDH
deserialization and frame detection functions. The
block diagram in Figure 4 shows the basic opera-
tion of the chip. This chip can be used to implement
the front end of SONET equipment, which consists
primarily of the serial transmit interface and the se-
rial receive interface. The chip includes serial-to-par-
allel conversion and system timing. The system
timing circuitry consists of management of the
datastream, framing, and clock distribution throughout
the front end.
Figure 4. S3064 Functional Block Diagram
1:16 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FPP/N
LLCLKP/N
LLDP/N
POUTP/N[15:0]
16
RSCLKP/N
LSCLKP/N
LSDP/N
SDPECL
M
U
X
POCLKP/N
D
D
D
LLEB
RSTB
SEARCH
FRAMEN
KILLRXCLK
RX155MCKP/N
Suggested Interface Devices
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S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
4
December 6, 1999 / Revision NC
RECEIVER OPERATION
The S3064 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 155.52 Mbyte/sec parallel data
format. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled and disabled by the
FRAMEN input. Detection is enabled by a rising edge
on OOF when FRAMEN is active. It is disabled when
a framing pattern is detected. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUTP/N[15:0]) will not
contain valid data. The timing generator block takes
the located byte boundary and uses it to block the
incoming data stream into bytes for output on the
parallel output data bus (POUTP/N[15:0]). The frame
boundary is reported on the frame pulse (FP) output
when any 32-bit pattern matching the framing pat-
tern is detected on the incoming data stream. When
framing pattern detection is disabled, the byte bound-
ary is frozen to the location found when detection
was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
s, even for extremely high bit error
rates.
Serial to Parallel Converter
The serial to parallel converter consists of three
16-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version. The second is an 16-bit internal holding
register, which transfers data from the serial to par-
allel register on byte boundaries as determined by
the frame and byte boundary detection block. On the
falling edge of the free running POCLK, the data in
the holding register is transferred to an output hold-
ing register which drives POUTP/N[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the serial-to-parallel block in place of the
normal data stream (RSCLK and RSD). When DLEB
is asserted, SDPECL shall be ignored.
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. When LLEB is active,
it enables the Line Loopback output data and clock
(LLD and LLCLK) and a receive-to-transmit loopback
can be established at the serial data rate.
5
S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
December 6, 1999 / Revision NC
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Table 2. Input Pin Assignment and Description
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