S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

BiCMOS LVPECL CLOCK GENERATOR

DEVICE
SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

S3067

FEATURES

· SiGe BiCMOS technology
· Complies with Bellcore and ITU-T

specifications

· On-chip high-frequency PLL for clock

generation

· Supports OC-48 (with FEC),

OC-24 (with FEC),
OC-12 (with FEC),
OC-3 (with FEC)

· FEC capability of up to 8 bytes per

255-byte block

· Reference frequency of 155.52 to 178 MHz
· Interface to LVPECL and TTL logic
· 16 Bit single-ended LVPECL data path
· Compact 156 TBGA package
· Diagnostic loopback mode
· Supports line timing
· Lock Detect
· Signal detect input
· Low jitter LVPECL interface
· Internal FIFO to decouple transmit clocks
· Single 3.3 V supply
· Typical power 1.5 W

APPLICATIONS

· Wavelength Division Multiplexing equipment
· SONET/SDH-based transmission systems
· SONET/SDH modules
· SONET/SDH test equipment

Figure 1. System Block Diagram

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

S3067

· ATM over SONET/SDH
· Section repeaters
· Add Drop Multiplexers (ADM)
· Broad-band cross-connects
· Fiber optic terminators
· Fiber optic test equipment

GENERAL DESCRIPTION

The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization
SONET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.

On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
155.52 to 178 MHz reference clock, in support of
existing system clocking schemes.

The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3067 is packaged in a 156
TBGA, offering designers a small package outline.

The S3067 supports FEC designs with internal divid-
ers or external clocking modes.

S3076

Clock

Recovery

Unit

S3062

Receive

S3062

Transmit

FEC Added

S3067

Transmit

Serialization

S3067

Receive

Deserialization

S3076

Clock

Recovery

Unit

S3062

Receive

FEC Data

Stripped Off

S3062

Transmit

S3067

Transmit

Serialization

S3067

Receive

Deserialization

2.488 Gbps

2.488

Gbps

155 Mbps

2.67 Gbps

X + Y

167 Mbps

X + Y

167 Mbps

X + Y

155 Mbps

X + Y

2.67 Gbps

2.488 Gbps

PERFORMANCE MONITOR

X = Data
Y = FEC Data

E/O

O/E

OPTICAL FIBER

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

SONET OVERVIEW

Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.

The SONET standard is a layered protocol with four
separate layers defined. These are:

· Photonic
· Section
· Line
· Path

Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.

Data Rates and Signal Hierarchy

Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport

signal level-1 (STS-1). An STS-

N signal is made up of

N byte-interleaved STS-1 signals. The optical counter-
part of each STS-

N signal is an optical carrier level-N

signal (OC-

N). The S3067 chip supports up to the OC-

48 rate with different FEC modes.

Frame and Byte Boundary Detection

The SONET/SDH fundamental frame format for
STS-48 consists of 144 transport overhead bytes
followed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 144 overhead and 4176 SPE
bytes is repeated nine times in each frame. Frame and
byte boundaries are detected using the A1 and A2
bytes found in the transport overhead. (See Figure 3.)

For more details on SONET operations, refer to the
Bellcore SONET standard document.

Elec.

CCITT

Optical Data Rate (Mbit/s)

STS-1

OC-1

51.84

STS-3

STM-1

OC-3

155.52

STS-12

STM-4

OC-12

622.08

STS-24

STM-8

OC-24

1244.16

STS-48 STM-16

OC-48 2488.32

Table 1. SONET Signal Hierarchy

Figure 2. SONET Structure

Figure 3. STS48/OC48 Frame Format

9 Rows

48 A1

Bytes

48 A2

Bytes

A1 A1

A2 A2

Transport Overhead 144 Columns
144 x 9 = 1296 bytes

Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes

125

sec

End Equipment

Payload to

SPE mapping

Maintenance,

protection,

switching

Optical

transmission

Scrambling,

framing

Fiber Cable

End Equipment

Section layer

Photonic layer

Line layer

Path layer

Section layer

Photonic layer

Line layer

Functions

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

S3067 OVERVIEW

The S3067 transceiver implements SONET/SDH
and WDM serialization/deserialization, and transmis-
sion functions. The block diagram in Figure 4 shows
the basic operation of the chip. This chip can be
used to implement the front end of WDM equipment,
which consists primarily of the serial transmit inter-
face and the serial receive interface. The chip
handles all the functions of these two elements, in-
cluding parallel-to-serial and serial-to-parallel
conversion, clock generation, and system timing.
The system timing circuitry consists of management
of the data stream and clock distribution throughout
the front end.

S3067 has ability to bypass the internal VCO with an
external source and also with the receive clock. The
device generates 14/15, 15/14, 16/17 and 17/16
clocks based upon the received clock and an exter-
nal clock to incorporate the FEC capability. The
dividers support the first two rates shown in Table 4.

The S3067 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:

Table 2. Data Rate Select

Transmitter Operations:

1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output

Receiver Operations:

1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output

Internal clocking and control functions are transpar-
ent to the user.

S3067 Supports six different code rates, besides the
normal rate, for each of the four operating modes.

)

(

Table 4. FEC Modes

Table 3. FEC Select

Suggested Interface Devices

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Figure 5. Clock Synthesizer

LPF

VCO

VCOCLK

REFCLK

FECSEL (0-1)

FECSEL 2

RSCLK

Where N = 14/15/16/17

M = 14/15/16/17

RSCLK N

VCOCLK M

RSCLK Divider

VCO Divider

A high on FECSEL2 selects RSCLK divided by N. A low on FECSEL2 selects the REFCLK. The REFCLK or
RSCLK divided by N is divided by 1/M (multiplied by M) in the loop. The value of M and N can be selected by
FECSEL0 and FECSEL1.

When FECSEL2 = 0, VCOCLK = REFCLK * M. The user must select the proper value of REFCLK and M to get
the desired VCOCLK frequency. When FECSEL2 = 1, VCOCLK = (RSCLK * M)

N. The user must select the

proper M/N ratio (with FECSEL0 and FECSEL1) to get the desired VCOCLK value. (See Tables 3 and 4.)

Example: OC-48 FEC capability of 8 bytes per 255-byte block. Required VCOCLK = 2.6656 GHz.

Method 1:

Required VCOCLK = 2.6656 GHz
FECSEL2 = 0, selects REFCLK
FECSEL0 = 1 and FECSEL1 = 0, selects VCO divider(M) = 16
REFCLK = 2.6656 GHz

16 = 166.60 MHz

VCOCLK = REFCLK

(1/M) = 166.60 * 16 = 2.6656 GHz

Method 2:

Required VCOCLK = 2.6656 GHz
FECSEL2 = 1, selects RSCLK
FECSEL0 = 0 and FECSEL1 = 0, selects VCO divider(M) = 17 and RSCLK divider(N) = 16
RSCLK = (2.6656 * 16)

17 = 2.5088 GHz

VCOCLK = RSCLK

(1/M) = 2.5088 GHz

16 * 17 = 2.6656 GHz.

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

S3067 TRANSCEIVER
FUNCTIONAL DESCRIPTION

TRANSMITTER OPERATION

The S3067 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48/STS-24/STS-12/STS-3/GBE data stream
depending on the data rate selected. It converts 16
bit parallel data to bit serial format.

A high-frequency bit clock can be generated from a
155.52 to 178 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.

Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
other operating modes.

The bypass signal selects between the BYPASSCLK
and the VCO clock. BYPASSCLK can be used to
provide an alternative clock to the internal VCO
when the user selects an error correcting capability
which is not provided by the S3067 dividers. The
user must provide the required frequency for the
BYPASSCLK when error correcting capability of 6/5/
4/3 bytes per 255-byte block is selected.

Clock Synthesizer

The clock synthesizer, shown in the block diagram in
Figures 4 and 5, is a monolithic PLL that generates
the serial output clock frequency locked to the input
Reference Clock (REFCLKP/N).

The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy of
better than the value stated in Table 10 in order for
the TSCLK frequency to have the same accuracy
required for operation in a SONET system. Lower
accuracy crystal oscillators may be used in applica-
tions less demanding than SONET/SDH.

The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.

The divide by 'N' and divide by 'M' provide the
counters required to support error correcting capabil-
ity. The values of 'N' and 'M' can be selected by
FECSEL lines.

The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.

Timing Generator

The timing generation function, seen in Figure 4,
provides a divide-by-16 version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[15:0] data from
the parallel input register to the serial shift register.

The PCLK output is a divide-by-16 rate version of
transmit serial clock (divide-by-16). PCLK is in-
tended for use as a divide-by-16 clock for upstream
multiplexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3067 device.

The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the reference clock REFCLK. The PLL in
the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the
internal clock with that of the Reference Clock
(REFCLK).

Table 5. Reference Jitter Limits

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Parallel-to-Serial Converter

The parallel-to-serial converter shown in Figure 4 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PIN[15:0]
bus on the rising edge of PICLK. The parallel-to-
serial register is a loadable shift register which takes
its parallel input from the FIFO output.

An internally generated divide-by-16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.

FIFO

A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated
divide-by-16 clock is used to clock out data from the
FIFO. PHINIT and LOCKDET are used to center or
reset the FIFO. The PHINIT and LOCKDET signals
will center the FIFO after the third PICLK pulse. This
is in order to insure that PICLK is stable. This
scheme allows the user to have an infinite PCLK to
PICLK delay through the ASIC. Once the FIFO is
centered, the PCLK to PICLK delay can have a
maximum drift specified by Table 20.

FIFO Initialization

The FIFO can be initialized in one of the following
three ways:

1.During power up, once the PLL has locked to the

reference clock provided on the REFCLK pins, the
LOCKDET will go active and initialize the FIFO.

2.When RSTB goes active, the entire chip is reset.

This causes the PLL to go out of lock and thus the
LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held reset when
RSTB is active.

3.The user can also initialize the FIFO by raising

PHINIT.

During the normal running operation, the incoming
data is passed from the PICLK timing domain to the
internally generated divide by 16 clock timing do-
main. Although the frequency of PICLK and the
internally generated clock is the same, their phase

relationship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated clock. When a potential setup or hold time
violation is detected, the phase error goes high.
When PHERR conditions occur, PHINIT should be
activated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs up to 10 bytes of
data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete.

RECEIVER OPERATION

The S3067 receiver chip provides the first stage of
digital processing of a receive SONET STS-48/STS-
24/STS-12/STS-3/GBE bit-serial stream. The bit
serial data stream is then converted into a 16 bit
half-word data format. A loopback mode is provided
for diagnostic loopback (transmitter to receiver). A
line loopback (receiver to transmitter) is also pro-
vided. Both line and local loopback modes can be
active at the same time.

Serial-to-Parallel Converter

The serial-to-parallel converter consists of two 16-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs the serial-to-parallel conversion
clocked by the clock recovery block. On the falling
edge of the POCLK, the data in the parallel register
is transferred to an output parallel register which
drives POUT[15:0].

OTHER OPERATING MODES

Diagnostic Loopback

When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal data stream
(RSD). TSD/TSCLK outputs are active. DLEB takes
precedence over SDPECL and SDTTL.

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Line Loopback

The line loopback circuitry selects the source of the
data and clock which is output on TSD and TSCLK.
When the Line Loopback Enable input (LLEB) is
high, it selects data and clock from the parallel-to-
serial converter block. When LLEB is low, it forces
the output data multiplexer to select the data and
clock from the RSD and RSCLK inputs, and a re-
ceive-to-transmit loopback can be established at the
serial data rate. Diagnostic loopback and line
loopback can be active at the same time.

Loop Timing

In Serial Loop Timing mode (SLPTIME), the clock
synthesizer PLL of the S3067 is bypassed, and the
timing of the entire transmitter section is controlled
by the Receive Serial Clock, RSCLKP/N. This mode
is entered by setting the SLPTIME input to a TTL
high level.

In this mode the REFCLKP/N input is not used, and
the RATESEL input is ignored for all transmit func-
tions. It should be carefully noted that the internal
PLL continues to operate in this mode, and contin-
ues as the source for the 19MCK and 155MCK, and
if these signals are being used (e.g. as the reference
for an external S3076 clock recovery device), the
REFCLKP/N and RATESEL inputs must be properly
driven.

In Reference Loop Timing mode (RLPTIME), the
Parallel Clock from the receiver (POCLK) is used as
the reference clock to the transmitter. In this mode,
the REFCLKP/N input is not used. The 19MCK and
155MCK are generated from the POCLK in this op-
erating mode. When operating the S3067 in
RLPTIME mode, the 19MCK and 155MCK outputs
should not be used as the back-up reference clock
for a clock and data recovery device (S3066,
S3040). When performing loopback testing (DLEB),
the S3067 must not be in RLPTIME.

"Squelched Clock" Operation

Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state if the optical signal is
removed or reduced below a fixed threshold. This
condition is accompanied by the expected
deassertion of the Signal Detect (SD) output.

The S3067 has been designed for operation with
clock recovery devices that provide continuous serial
clock for seamless downstream clocking in the event
of optical signal loss.

For operation with an optical transceiver that pro-
vides the "squelched clock" behavior as described
above, the S3067 can be operated in the "squelched
clock" mode by activating the SQUELCH pin.

In this condition, the Receive Serial Clock (RSCLKP/N)
is used for all receiver timing when the SDLVPECL/
SDTTL inputs are in the active state. When the
SDLVPECL/SDTTL inputs are placed in the inactive
state (usually by the deassertion of LOCKDET or Sig-
nal Detect from the optical transceiver/clock recovery
unit) the transmitter serial clock will be used to maintain
timing in the receiver section. This will allow the
POCLK to continue to run and the parallel outputs to
flush out the last received characters and then assume
the all zero state imposed at the serial data input.

It is important to note that in this mode there will be
a one time shortening or lengthening of the POCLK
cycle, resulting in an apparent phase shift in the
POCLK at the deassertion of the SD condition. An-
other similar phase shift will occur when the SD
condition is reasserted.

In the normal operating mode with SQUELCH inac-
tive, there will be no phase discontinuities at the
POCLK output during signal loss or reacquisition
(assuming operation with continuous clocking from
the CRU device such as the AMCC S3076).

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Table 6. S3067 Transmitter Pin Assignment and Descriptions

(

]

[

]

[

)

(

]

[

)

]

[

]

[

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Table 7. S3067 Receiver Pin Assignment and Descriptions

)

(

)

(

)

(

]

[

]

[

]

[

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Table 8. S3067 Common Pin Assignment and Descriptions

)

(

)

(

)

(

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Table 8. S3067 Common Pin Assignment and Descriptions (Continued)

)

(

]

[

(

)

(

)

(

)

(

)

(

)

(

)

(

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Figure 6. S3067 Pinout-Bottom View

156 TBGA

BOTTOM VIEW

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Figure 7. S3067 Pinout-Top View

156 TBGA

TOP VIEW

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Table 12. Recommended Operating Conditions

Table 11. Absolute Maximum Ratings

Table 10. Performance Specifications

)

(

)

(

ESD Ratings
The S3067 is rated to the following voltages based on the human body model:
1. All pins are rated above 200 V.

1. Outputs unterminated.

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Table 13. LVTTL Input/Output DC Characteristics

Table 14. Internally Biased Differential LVPECL Input DC Characteristics

Table 15. Differential LVPECL Output DC Characteristics

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Table 16. Single-Ended LVPECL Input DC Characteristics

Table 17. Single-Ended LVPECL Output DC Characteristics

(

)

(

)

1. The AMCC LVPECL inputs (V

and V

) are non-temperature compensated I/O which vary at 1.3 mV/°C

1. The AMCC LVPECL outputs are non-temperature compensated I/O which vary at 1.3 mV/°C

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Table 18. CML Output DC Characteristics

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

Table 19. CML Input DC Characteristics

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000/ Revision A

Figure 9. Transmitter Input Timing

Figure 10. Transmitter Output Timing

PICLKP

PIN[15:0]

TSCLKP

TSD

tSTSD

tHTSD

Table 20. Transmitter AC Timing Characteristics

)

(

)

(

]

[

)

(

]

[

)

(

)

(

Notes on High-Speed Timing:
1. Timing is measured from the cross-over point of the reference signal to the 50% level of the input/output.

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Table 21. AC Receiver Timing Characteristics

]

[

)

(

)

(

]

[

)

(

)

(

]

[

)

(

)

(

]

[

)

(

)

(

Figure 12. Receiver Output Timing Diagram

Figure 11. Receiver Input Timing Diagram

Notes on High-Speed LVPECL Input Timing:

1. Timing is measured from the cross-over point of the reference signal to the 50% level of the output.

RSD

RSCLKP

POUT

POCLKP

POUT[15:0]

S3067

MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER WITH FEC

October 26, 2000 / Revision A

Ordering Information

AMCC is a registered trademark of Applied Micro Circuits Corporation.

D159/R250

AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.

AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.

AMCC reserves the right to ship devices of higher grade in place of those of lower grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Applied Micro Circuits Corporation · 6290 Sequence Dr., San Diego, CA 92121

Phone: (858) 450-9333 · (800) 755-2622 · Fax: (858) 450-9885

http://www.amcc.com

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