Part Number S3092

Revision A February 22, 2002

DEVICE SPECIFICATION

S3092

SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp

FEATURES

Silicon Germanium BiCMOS technology

Complies with Telcordia, ITU-T, and G.709
specifications

Integrated Phase Lock Loop

OC-192 with FEC and Digital Wrapper (DW)
(9.953 to 10.709 Gbps)

Reference frequency of 155.52 MHz
(or equivalent FEC or DW rate)

16-bit parallel, 622.08 Mbps (or equivalent FEC
or DW rate) LVDS data path

Lock detect

Low jitter CML differential serial interface

Dual +3.3 V and -5.2 V power supply

Performs clock recovery for 9.953 Gbps
(or equivalent FEC or DW rate) serial NRZ data

Synthesizes parallel output clock during loss-
of-signal conditions

Postamp on serial input

148-pin CBGA package

Typical power dissipation 2.2 W

APPLICATIONS

SONET/SDH-based transmission systems

SONET/SDH modules

SONET/SDH test equipment

ATM over SONET/SDH

Section repeaters

Add Drop Multiplexers (ADM)

Broad-band cross-connects

Fiber optic terminators

Fiber optic test equipment

GENERAL DESCRIPTION

The S3092 SONET/SDH receiver chip is a fully inte-
grated deserializer/CDR with SONET OC-192 with FEC
and Digital Wrapper (9.953 Gbps to 10.709 Gbps) rate
capability. The S3092 receives an OC-192 scrambled
NRZ signal and recovers the clock from the data. The
chip performs all necessary serial-to-parallel functions in
conformance with SONET/SDH/Digital Wrapper trans-
mission standards. The device is suitable for SONET-
based ATM applications. Figure 1 shows a typical net-
work application.

The S3092 is a fully integrated OC-192/STM-64 Clock
and Data Recovery (CDR) and demultiplexer (DeMUX).
The S3092 recovers a synchronous signal from the
incoming 9.953 Gbps to 10.709 Gbps serial NRZ data
stream and re-times and demultiplexes the serial data
into 16 parallel 622.08 Mbps (or equivalent FEC or DW
rate) lines. The IC detects a Loss-of-Signal condition,
outputs a stable 622.08 MHz (or equivalent FEC or DW
rate) clock when the serial data is lost, and provides
1:16 demultiplexing. It also has a limiting postamp on
the serial input for small signal gain.

The chip can be used with a 155.52 MHz (or equiva-
lent FEC or DW rate) reference clock. The low jitter
LVDS interface guarantees compliance with the bit-
error rate requirements of the Bellcore and ITU-T
standards.

Figure 1. System Block Diagram

ORX

OTX

ORX

OTX

S3091

S3092

S3091

INDUS

(19201),

GANGES

(19202)

HUDSON

(19203)

INDUS

(19201),

GANGES

(19202)

HUDSON

(19203)

S3092 SONET/SDH/ATM OC-192 1:16
Receiver with CDR and Postamp

Revision A February 22, 2002

DEVICE SPECIFICATION

CONTENTS

FEATURES .............................................................................................................................................................. 1

APPLICATIONS ...................................................................................................................................................... 1

GENERAL DESCRIPTION ...................................................................................................................................... 1

CONTENTS ............................................................................................................................................................. 2

LIST OF FIGURES .................................................................................................................................................. 3

LIST OF TABLES .................................................................................................................................................... 3

SONET OVERVIEW ................................................................................................................................................ 4

Data Rates and Signal Hierarchy ...................................................................................................................... 4

Frame and Byte Boundary Detection ................................................................................................................ 4

S3092 OVERVIEW .................................................................................................................................................. 6

S3092 ARCHITECTURE/FUNCTIONAL DESIGN .................................................................................................. 7

Receiver Description ......................................................................................................................................... 7

Postamp ............................................................................................................................................................ 7

Clock Recovery ................................................................................................................................................. 7

Lock Detect ........................................................................................................................................................ 7

Serial-to-Parallel Converter ............................................................................................................................... 7

Power Sequencing ............................................................................................................................................ 7

Ordering Information ........................................................................................................................................... 21

S3092 SONET/SDH/ATM OC-192 1:16
Receiver with CDR and Postamp

Revision A February 22, 2002

DEVICE SPECIFICATION

LIST OF FIGURES

Figure 1. System Block Diagram ............................................................................................................................. 1

Figure 2. SONET Structure ...................................................................................................................................... 4

Figure 3. STS-192 Frame Format ............................................................................................................................ 5

Figure 4. Functional Block Diagram ......................................................................................................................... 6

Figure 5. S3092 Pinout .......................................................................................................................................... 11

Figure 6. S3092 Package ...................................................................................................................................... 12

Figure 7. Parallel Data Output Delay from POCLK ................................................................................................ 17

Figure 8. Data Invalid Window ............................................................................................................................... 18

Figure 9. S3092 LVDS Driver to LVDS Input, Reference Only .............................................................................. 18

Figure 10. -5.2 V ECL Post Amp to S3092 Input DC Coupled Termination, Reference Only ................................ 19

Figure 11. -5.2 V ECL Post Amp to S3092 Input AC Coupled Termination, Reference Only ................................ 19

Figure 12. External Loop Filter ............................................................................................................................... 19

Figure 13. Differential Voltage Measurement ........................................................................................................ 20

Figure 14. Jitter Tolerance UIpp ............................................................................................................................ 20

LIST OF TABLES

Table 1. SONET Signal Hierarchy ........................................................................................................................... 4

Table 2. Input Pin Description and Assignment ....................................................................................................... 8

Table 3. Output Pin Description and Assignment .................................................................................................... 9

Table 4. Common Pin Description and Assignment ............................................................................................... 10

Table 5. Thermal Management .............................................................................................................................. 12

Table 6. Performance Specifications ..................................................................................................................... 13

Table 7. Absolute Maximum Ratings ..................................................................................................................... 14

Table 8. Recommended Operating Conditions ...................................................................................................... 14

Table 9. Internally Biased Differential CML Input DC Characteristics .................................................................... 15

Table 10. Single-Ended ECL Input DC Characteristics .......................................................................................... 15

Table 11. LVDS Output DC Characteristics ........................................................................................................... 15

Table 12. LVTTL Input DC Characteristics ............................................................................................................ 15

Table 13. LVTTL Output DC Characteristics ......................................................................................................... 16

Table 14. AC Characteristics ................................................................................................................................. 16

Table 15. Internally Biased Differential ECL Input DC Characteristics .................................................................. 17

Table 16. External Loop Filter Components .......................................................................................................... 17

Table 17. FEC Modes ............................................................................................................................................ 18

S3092 SONET/SDH/ATM OC-192 1:16
Receiver with CDR and Postamp

Revision A February 22, 2002

DEVICE SPECIFICATION

SONET OVERVIEW

Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber intercon-
n e c t b e tw e e n te l e p h o n e n e t w o r k s o f d iff e re n t
countries. SONET is capable of accommodating a
variety of transmission rates and applications.

The SONET standard is a layered protocol with four
separate layers defined. These are:

· Photonic

· Section

· Line

· Path

Figure 2 shows the layers and their functions. Each of
the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for trans-
mitting the electrical signals in optical form over the
physical media. The section layer handles the trans-
port of the framed electrical signals across the optical
cable from one end to the next. Key functions of this
layer are framing, scrambling, and error monitoring.
The line layer is responsible for the reliable transmis-
sion of the path layer information stream carrying
voice, data, and video signals. Its main functions are
synchronization, multiplexing, and reliable transport.
The path layer is responsible for the actual transport of
services at the appropriate signaling rates.

Data Rates and Signal Hierarchy

Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is
the basic SONET signal referred to as the synchro-
nous transport signal level-1 (STS-1). An STS-N
signal is made up of N byte-interleaved STS-1 sig-
nals. The optical counterpart of each STS-N signal
is an optical carrier level-N signal (OC-N). The chip
supports OC-192 with FEC and Digital Wrapper
(9.95328 Gbps to 10.709 Gbps) rates.

Frame and Byte Boundary Detection

The SONET/SDH fundamental frame format for STS-
192 consists of 576 transport overhead bytes followed
by Synchronous Payload Envelope (SPE) bytes. This
pattern of 576 overhead and 16,704 SPE bytes is
repeated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.) The
S3092 does not provide A1/A2 detection or alignment
to.

For more details on SONET operations, refer to the
Bellcore SONET standard document.

Figure 2. SONET Structure

Table 1. SONET Signal Hierarchy

Elec.

ITU-T

Optical

Data Rate

(Mbps)

STS-1

OC-1

51.84

STS-3

STM-1

OC-3

155.52

STS-12

STM-4

OC-12

622.08

STS-24

STM-8

OC-24

1244.16

STS-48

STM-16

OC-48

2488.32

STS-192

STM-64

OC-192

9953.28

Path layer

Line layer

Section layer

Functions

Maintenance,
protection,
switching

Scrambling,
framing

Optical
transmission

Payload to
SPE mapping

Photonic layer

Path layer

Line layer

Fibre Cable

Section layer

Photonic layer

End Equipment

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