Document Outline
- About this Document
- Table of Contents
- Architectural Overview
- Signal Descriptions
- PCI Configuration Registers
- PCI Bus Operation Registers
- Add-On Bus Operation Registers
- Initialization
- PCI Bus Interface
- Add-On Bus Interface
- Mailbox Overview
- FIFO Overview
- Pass-Thru Overview
- Electrical Characteristics
- Pinout and Package Information
S5935
PCI PRODUCT
DATA BOOK
For Marketing and Application Information Contact:
Applied Micro Circuits Corporation
6290 Sequence Drive
San Diego, CA 92121-4358
(800) 755-2622
(619) 450-9333
Fax (619) 450-9885
http://www.amcc.com
A
PPLIED
M
ICRO
C
IRCUITS
C
ORPORATION
The material in this document supersedes
all previous documentation issued for any
of the products included herein.
Copyright 1999 Applied Micro Circuits Corporation
PRINTED IN U.S.A./PCIPROD-1299
AMCC reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is
current.
AMCC does not assume any liability arising out of the application or
use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of
those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED,
INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR
OTHER CRITICAL APPLICATIONS.
AMCC and Matchmaker are registereded trademarks of Applied Micro
Circuits Corporation.
All other product names are trademarks, registered trademarks, or
servicemarks of their respective owners.
i
1. ARCHITECTURAL OVERVIEW ............................................................................................................... 1-1
Introduction to the PCI Local Bus ......................................................................................................... 1-1
S5935 Architecture ................................................................................................................................ 1-2
S5935 Register Architecture ................................................................................................................. 1-2
PCI Configuration Registers ................................................................................................................. 1-2
PCI Operation Registers ....................................................................................................................... 1-3
Add-On Bus Operation Registers ......................................................................................................... 1-3
Non-Volatile Memory Interface .............................................................................................................. 1-3
Mailbox Operation ................................................................................................................................. 1-4
Pass-Thru Operation ............................................................................................................................. 1-5
FIFO PCI Bus Mastering Operation ...................................................................................................... 1-5
2. SIGNAL DESCRIPTIONS ......................................................................................................................... 2-9
Signal Type Definition ........................................................................................................................... 2-9
Address and Data Pins PCI Local Bus ............................................................................................ 2-10
PCI Bus Interface Signals ................................................................................................................... 2-10
System Pins PCI Local Bus .............................................................................................................. 2-11
Interface Control Pins PCI Bus Signal ................................................................................... 2-11
Arbitration Pins (Bus Masters Only) PCI Local Bus .............................................................. 2-12
Error Reporting Pins PCI Local Bus ..................................................................................... 2-12
Interrupt Pin PCI Local Bus .................................................................................................. 2-12
Non-Volatile Memory Interface Signals ............................................................................................... 2-13
Serial nv Devices ..................................................................................................................... 2-13
Byte-Wide nv Devices ............................................................................................................. 2-13
Add-On Bus Interface Signals ............................................................................................................. 2-14
Register Access Pins ............................................................................................................... 2-14
FIFO Access Pins .................................................................................................................... 2-15
Pass-Thru Interface Pins ......................................................................................................... 2-15
System Pins ............................................................................................................................. 2-16
3. PCI CONFIGURATION REGISTERS ..................................................................................................... 3-17
PCI Configuration Space Header ........................................................................................................ 3-18
Vendor Identification Register (VID) .................................................................................................... 3-19
Device Identification Register (DID) .................................................................................................... 3-20
PCI Command Register (PCICMD) .................................................................................................... 3-21
PCI Status Register (PCISTS) ............................................................................................................ 3-23
Revision Identification Register (RID) ................................................................................................. 3-25
Class Code Register (CLCD) .............................................................................................................. 3-26
Cache Line Size Register (CALN) ...................................................................................................... 3-30
Latency Timer Register (LAT) ............................................................................................................. 3-31
Header Type Register (HDR) .............................................................................................................. 3-32
Built-in Self-Test Register (BIST) ........................................................................................................ 3-33
Base Address Registers (BADR) ........................................................................................................ 3-34
Expansion ROM Base Address Register (XROM) .............................................................................. 3-38
Interrupt Line Register (INTLN) ........................................................................................................... 3-40
Interrupt PIN Register (INTPIN) .......................................................................................................... 3-41
C
ONTENTS
ii
Minimum Grant Register (MINGNT) ................................................................................................... 3-42
Maximum Latency Register (MAXLAT) ............................................................................................... 3-43
4. PCI BUS OPERATION REGISTERS ...................................................................................................... 4-45
Outgoing Mailbox Registers (OMB) .................................................................................................... 4-46
Incoming Mailbox Registers (IMB) ...................................................................................................... 4-46
FIFO Register Port (FIFO) .................................................................................................................. 4-46
PCI Controlled Bus Master Write Address Register (MWAR) ............................................................. 4-47
PCI Controlled Bus Master Write Transfer Count Register (MWTC) .................................................. 4-48
PCI Controlled Bus Master Read Address Register (MRAR) ............................................................. 4-49
PCI Controlled Bus Master Read Transfer Count Register (MRTC) ................................................... 4-50
Mailbox Empty Full/Status Register (MBEF) ....................................................................................... 4-51
Interrupt Control/Status Register (INTCSR) ........................................................................................ 4-53
Master Control/Status Register (MCSR) ............................................................................................. 4-57
5. ADD-ON BUS OPERATION REGISTERS ............................................................................................. 5-61
Add-On Incoming Mailbox Registers (AIMBx) .................................................................................... 5-62
Add-On Outgoing Mailbox Registers (AOMBx) ................................................................................... 5-62
Add-On FIFO Register Port (AFIFO) .................................................................................................. 5-62
Add-On Controlled Bus Master Write Address Register (MWAR) ....................................................... 5-63
Add-On Pass-Thru Address Register (APTA) ..................................................................................... 5-64
Add-On Pass-Thru Data Register (APTD) .......................................................................................... 5-64
Add-On Controlled Bus Master Read Address Register (MRAR) ....................................................... 5-65
Add-On Empty/Full Status Register (AMBEF) .................................................................................... 5-66
Add-On Interrupt Control/Status Register (AINT) ............................................................................... 5-68
Add-On General Control/Status Register (AGCSTS) ......................................................................... 5-71
Add-On Controlled Bus Master Write Transfer Count Register (MWTC) ............................................ 5-74
Add-On Controlled Bus Master Read Transfer Count Register (MRTC) ............................................ 5-75
6. INITIALIZATION ..................................................................................................................................... 6-77
PCI Reset ............................................................................................................................................ 6-77
Loading From Byte-wide nv Memories ............................................................................................... 6-77
Loading From Serial nv Memories ...................................................................................................... 6-78
PCI Bus Configuration Cycles ............................................................................................................. 6-80
Expansion BIOS ROMs ...................................................................................................................... 6-82
7. PCI BUS INTERFACE ............................................................................................................................ 7-85
PCI Bus Transactions ......................................................................................................................... 7-86
PCI Burst Transfers ................................................................................................................. 7-86
PCI Read Transfers ................................................................................................................. 7-88
PCI Write Transfers ................................................................................................................. 7-89
Master-Initiated Termination .................................................................................................... 7-89
Normal Cycle Completion ........................................................................................................ 7-89
Initiator Preemption ................................................................................................................. 7-90
Master Abort ............................................................................................................................ 7-91
Target-Initiated Termination ..................................................................................................... 7-91
iii
Target Disconnects .................................................................................................................. 7-92
Target Requested Retries ........................................................................................................ 7-93
Target Aborts ........................................................................................................................... 7-93
PCI Bus Mastership ........................................................................................................................... 7-95
Bus Mastership Latency Components ..................................................................................... 7-95
Bus Arbitration ......................................................................................................................... 7-95
Bus Acquisition ........................................................................................................................ 7-96
Target Latency ......................................................................................................................... 7-96
Target Locking ......................................................................................................................... 7-96
PCI Bus Interrupts ............................................................................................................................... 7-98
PCI Bus Parity Errors .......................................................................................................................... 7-98
8. ADD-ON BUS INTERFACE .................................................................................................................... 8-99
Add-On Operation Register Accesses ................................................................................................ 8-99
Add-On Interface Signals ........................................................................................................ 8-99
System Signals ........................................................................................................................ 8-99
Register Access Signals .......................................................................................................... 8-99
Asynchronous Register Accesses ......................................................................................... 8-100
Synchronous FIFO and Pass-Thru Data Register Accesses ................................................. 8-100
nv Memory Accesses Through the Add-On General Control/Status Register ....................... 8-100
Mailbox Bus Interface ....................................................................................................................... 8-100
Mailbox Interrupts .................................................................................................................. 8-103
FIFO Bus Interface ............................................................................................................................ 8-103
FIFO Direct Access Inputs ..................................................................................................... 8-103
FIFO Status Signals .............................................................................................................. 8-103
FIFO Control Signals ............................................................................................................. 8-103
Pass-Thru Bus Interface ................................................................................................................... 8-103
Pass-Thru Status Indicators .................................................................................................. 8-104
Pass-Thru Control Inputs ....................................................................................................... 8-104
Non-Volatile Memory Interface .......................................................................................................... 8-104
Non-Volatile Memory Interface Signals ................................................................................. 8-104
Accessing Non-Volatile Memory ............................................................................................ 8-105
nv Memory Device Timing Requirements .............................................................................. 8-107
9. MAILBOX OVERVIEW ......................................................................................................................... 9-109
Functional Description ...................................................................................................................... 9-109
Mailbox Empty/Full Conditions ............................................................................................... 9-110
Mailbox Interrupts ................................................................................................................... 9-110
Add-On Outgoing Mailbox 4, Byte 3 Access ........................................................................... 9-110
Bus Interface ...................................................................................................................................... 9-111
PCI Bus Interface ................................................................................................................... 9-111
Add-On Bus Interface ............................................................................................................. 9-111
8-Bit and 16-Bit Add-On Interfaces ......................................................................................... 9-111
Configuration ...................................................................................................................................... 9-112
Mailbox Status ........................................................................................................................ 9-112
Mailbox Interrupts ................................................................................................................... 9-113
PDF 
ZIP