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Table of Contents
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TABLE OF CONTENTS
PREFACE
INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
PURPOSE OF THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
INTENDED AUDIENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
USER'S MANUAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
AMD DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
E86 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
CHAPTER 1
FEATURES AND PERFORMANCE
1.1
KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
DISTINCTIVE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3
APPLICATION CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.2
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
CHAPTER 2
PROGRAMMING
2.1
REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
MEMORY ORGANIZATION AND ADDRESS GENERATION . . . . . . . . . 2-3
2.3
I/O SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4
INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5
SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.6
DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7
ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
CHAPTER 3
SYSTEM OVERVIEW
3.1
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.2
BUS OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.3
BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.1
Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.2
Static Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.3
Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.3.4
Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . . 3-24
3.4
CLOCK AND POWER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . 3-25
3.4.1
Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.2
Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.3
External Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.4.4
System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.4.5
Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
Peripheral Control Block Relocation Register
(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.2
Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . . 4-4
4.1.3
Processor Release Level Register (PRL, Offset F4h) . . . . . . . . . . 4-5
4.1.4
Auxiliary Configuration Register (AUXCON, Offset F2h). . . . . . . . 4-6
4.1.5
System Configuration Register (SYSCON, Offset F0h) . . . . . . . . 4-7
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