ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 22140
Rev: A Amendment/0
Issue Date: April 1998
Am29LV010B
1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
-- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
-- Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s
Manufactured on 0.35 m process technology
s
High performance
-- Full voltage range: access times as fast as 55 ns
-- Regulated voltage range: access times as fast
as 45 ns
s
Ultra low power consumption (typical values at
5 MHz)
-- 200 nA Automatic Sleep mode current
-- 200 nA standby mode current
-- 7 mA read current
-- 15 mA program/erase current
s
Flexible sector architecture
-- Eight 16 Kbyte
-- Supports full chip erase
-- Sector Protection features:
Hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Unlock Bypass Mode Program Command
-- Reduces overall programming time when
issuing multiple program command sequences
s
Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 1,000,000 write cycle guarantee per
sector
s
Package option
-- 32-pin TSOP
-- 32-pin PLCC
s
Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power supply Flash
-- Superior inadvertent write protection
s
Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
s
Erase Suspend/Erase Resume
-- Supports reading data from or programming
data to a sector that is not being erased
Am29LV010B
2
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV010B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV010B has a uniform sector architecture.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in standard EPROM
programmers.
The standard Am29LV010B offers access times of 45,
55, 70, and 120 ns (90 and 100 ns parts are also avail-
able), allowing high speed microprocessors to operate
without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single power supply (2.7
V3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
3
Am29LV010B
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
Family Part Number
Am29LV010B
Speed Options
Regulated Voltage Range: V
CC
=3.03.6 V
-45R
Full Voltage Range: V
CC
= 2.73.6 V
-55
-70
-120
Max access time, ns (t
ACC
)
45
55
70
120
Max CE# access time, ns (t
CE
)
45
55
70
120
Max OE# access time, ns (t
OE
)
30
30
35
50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
DQ7
Sector Switches
Data
Latch
Y-Gating
Cell Matrix
A
ddr
ess
La
tch
A0A16
22140A-1
Am29LV010B
4
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A11
A4
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
OE#
A3
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
32-Pin Reverse TSOP
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32-Pin Standard TSOP
22140A-2
DQ6
NC
DQ5
DQ4
DQ3
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17 18 19 20
16
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
V
CC
WE#
NC
DQ1
DQ2
V
SS
PLCC
5
Am29LV010B
A D V A N C E I N F O R M A T I O N
PIN CONFIGURATION
A0A16
=
17 addresses
DQ0DQ7 =
8 data inputs/outputs
CE#
=
Chip enable
OE#
= Output
enable
WE#
=
Write enable
V
CC
=
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
V
SS
=
Device ground
NC
=
Pin not connected internally
LOGIC SYMBOL
22140A-3
17
8
DQ0DQ7
A0A16
CE#
OE#
WE#
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