ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21545
Rev: A Amendment/+2
Issue Date: March 1998
Refer to AMD's Website (www.amd.com) for the latest information.
Am29SL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
-- 1.8 to 2.2 V for read, program, and erase
operations
-- Ideal for battery-powered applications
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Manufactured on 0.35 m process technology
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High performance
-- Access times as fast as 170 ns
s
Ultra low power consumption (typical values at
5 MHz)
-- 65 nA Automatic Sleep Mode current
-- 65 nA standby mode current
-- 5 mA read current
-- 10 mA program/erase current
s
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
-- One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
-- Supports full chip erase
-- Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
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Unlock Bypass Program Command
-- Reduces overall programming time when
issuing multiple program command sequences
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Top or bottom boot block configurations
available
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Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies data at specified addresses
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Minimum 1,000,000 write cycle guarantee per
sector
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Package option
-- 48-pin TSOP
-- 48-ball FBGA
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Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power supply Flash
-- Superior inadvertent write protection
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Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
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Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting
program or erase cycle completion
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Erase Suspend/Erase Resume
-- Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data
2
Am29SL800B
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29SL800B is an 8 Mbit, 1.8 V volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-pin TSOP and 48-
ball FBGA packages. The word-wide data (x16)
appears on DQ15DQ0; the byte-wide (x8) data
appears on DQ7DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
volt V
CC
supply. No V
PP
is for write or erase operations.
The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 170 or 200
ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 1.8 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo-
rithm--an internal algorithm that automatically prepro-
grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
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