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Электронный компонент: AAM79C981JC

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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
Publication# 17306 Rev: B Amendment/0
Issue Date: January 1999
1-71
Am79C981
Integrated Multiport Repeater PlusTM (IMR+TM)
DISTINCTIVE CHARACTERISTICS
s
Enhanced version of AMD's Am79C980
Integrated Multiport RepeaterTM (IMRTM) chip
with the following enhancements:
-- Additional management port features
--
Minimum
mode provides support for an extra
four LED outputs per port for additional status in
non-intelligent repeater designs
-- Pin/socket-compatible with the Am79C980
IMR chip
-- Fully backward-compatible with existing IMR
device designs
s
Interfaces directly with the Am79C987 HIMIBTM
device to build a fully managed multiport
repeater
s
CMOS device features high integration and low
power with a single +5 V supply
s
Repeater functions comply with IEEE 802.3
Repeater Unit specifications
s
Eight integral 10BASE-T transceivers utilize the
required predistortion transmission technique
s
Attachment unit interface (AUI) port allows
connectivity with 10BASE-5 (Ethernet) and
10BASE-2 (Cheapernet) networks, as well as
10BASE-F and/or Fiber Optic Inter-Repeater
Link (FOIRL) segments
s
On-board PLL, Manchester encoder/decoder,
and FIFO
s
Expandable to increase number of repeater
ports
s
All ports can be separately isolated (partitioned)
in response to excessive collision conditions or
fault conditions
s
Network management and optional features are
accessible through a dedicated serial
management port
s
Twisted-pair Link Test capability conforming to
the 10BASE-T standard. The receive Link Test
function can be optionally disabled through the
management port to facilitate interoperability
with devices that do not implement the Link Test
function
s
Programmable option of Automatic Polarity
Detection and Correction permits automatic
recovery due to wiring errors
s
Full amplitude and timing regeneration for
retransmitted waveforms
s
Preamble loss effects eliminated by deep FIFO
GENERAL DESCRIPTION
The Integrated Multiport Repeater Plus (IMR+) chip is a
VLSI circuit that provides a system-level solution to de-
signing a compliant 802.3 repeater incorporating
10BASE-T transceivers. The device integrates the
Repeater functions specified by Section 9 of the IEEE
802.3 standard and Twisted-Pair Transceiver functions
complying with the 10BASE-T standard. The Am79C981
provides eight integral twisted-pair medium attachment
units (MAUs) and an attachment unit interface (AUI) port
in an 84-pin plastic leaded chip carrier (PLCC).
A network based on the 10BASE-T standard uses un-
shielded twisted-pair cables, thereby providing an eco-
nomical solution to networking by allowing the use of
low-cost unshielded twisted-pair (UTP) cable or existing
telephone wiring.
The total number of ports per repeater unit can be in-
creased by connecting multiple IMR+ devices through
their expansion ports, minimizing the total cost per re-
peater port. Furthermore, a general-purpose attach-
ment unit interface (AUI) provides connection capability
to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet)
coaxial networks, as well as 10BASE-F and/or Fiber
Optic Inter-Repeater Link (FOIRL) fiber segments. Net-
work management and test functions are provided
through TTL-compatible I/O pins.
The IMR+ device interfaces directly with AMD's
Am79C987 Hardware Implemented Management In-
formation BaseTM (HIMIB) chip to build a fully managed
multiport repeater as specified by the IEEE 802.3
(Layer Management for 10 Mb/s Baseband Repeaters)
standard. When the IMR+ and HIMIB devices are
interconnected, complete repeater and per-port statis-
tics are maintained and can be accessed on demand
using a simple 8-bit parallel interface.

AMD
PRELIMINARY
172
Am79C981
For application examples on building a fully managed
repeater using the IMR+ and HIMIB devices, refer to
AMD's IEEE 802.3 Repeater Technical Manual
(PID#17314A) and the ISA-HUB
TM
User Manual
(PID # 17642A).
The device is fabricated in CMOS technology and re-
quires a single +5 V supply.
BLOCK DIAGRAM
RX
MUX
Phase =
Locked
Loop
FIFO
FIFO
Control
Preamble
Jam Sequence
Manchester
Encoder
IMR+ Chip
Control
Partitioning
Link Test
Timers
Manchester
Decoder
AUI
Port
DI
CI
DO
TP
Port
0
RXD
TXD
TXP
TP
Port
7
RXD
TXD
TXP
Reset
Clock
Gen
X1
X2
Expansion Port
REQ
ACK
COL
DAT
JAM
Test
and
Management
Port
SI
SO
RST
SCLK
TEST
CRS
STR
TX
MUX
17306B-1
RELATED AMD PRODUCTS
Part No. Description
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C987 Hardware Implemented Management Information Base
TM
(HIMIB
TM
)
Am79C940 Media Access Controller for Ethernet (MACE
TM
)
Am7990 Local Area Network Controller for Ethernet (LANCE)
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C900 Integrated Local Area Communications Controller
TM
(ILACC
TM
)
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA
+
Single-Chip Ethernet Controller for ISA (with Microsoft
Plug n' Play
Support)
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller
Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C981 173
P R E L I M I N A R Y
CONNECTION DIAGRAM
PLCC
DV
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
75
76
77
78
79
80
81
82
83
84
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
RXD0+
TXD6+
TXD6
TXP6+
TXP6
TXD4
TXD4+
TXP4+
TXP4
TXD0+
TXD0
TXP1+
TXP1
TXD2+
TXD2
TXP2+
TXP2
RXD0
RXD2+
RXD4+
RXD6+
RXD2
RXD4
RXD6
RXD7+
RXD7
TXD7+
TXD7
DV
SS
TXP7
TXP7+
DV
DD
TXD5
TXP5+
TXP5
TXD5+
DV
SS
TXP3
SO
DV
SS
STR
DV
DD
CRS
SI
SCLK
TEST
RST
DV
SS
X
1
X
2
ACK
COL
JAM
DAT
REQ
DV
SS
DV
DD
DV
SS
DO
DO+
DV
SS
DV
DD
TXD1+
TXD1
TXP1+
TXP1
TXD3+
TXD3
TXP3+
DV
DD
DV
SS
CI+
CI
DI+
DI
AV
SS
RXD1+
RXD1
RDX3+
RXD3
AV
DD
RXD5+
RXD5
IMR+ Chip
Am79C981
17306B-2

AMD
PRELIMINARY
174
Am79C981
LOGIC SYMBOL
DO+
DO
DI+
DI
CI+
CI
SCLK
X1
TEST
RST
DV
SS
AV
SS
STR
CRS
JAM
DAT
TXD+
TXP+
TXD
TXP
RXD+
RXD
DV
DD
AV
DD
Am79C981
AUI
Twisted Pair
Ports
(8 Ports)
SI
SO
ACK
COL
REQ
Expansion
Port
Port
Activity
Monitor
Management
Port
17306B-3
X2
LOGIC DIAGRAM
AUI
Management
Port
Expansion
Port
Twisted Pair
Port 0
Twisted Pair
Port 7
17306B-4
Repeater
State
Machine
Am79C981 175
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.
Valid Combinations
Valid combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C981 J C
DEVICE NUMBER/DESCRIPTION
Am79C981
Integrated Multiport Repeater Plus (IMR+)
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0
C to +70
C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
SPEED
Not Applicable
Valid Combinations
Am79C981 JC