Document Outline
- Am79C984A
- DISTINCTIVE CHARACTERISTICS
- GENERAL DESCRIPTION
- ORDERING INFORMATION
- BLOCK DIAGRAM
- RELATED AMD PRODUCTS
- TABLE OF CONTENTS
- CONNECTION DIAGRAM
- LOGIC SYMBOL
- LOGIC DIAGRAM
- PIN DESIGNATIONS
- PIN DESCRIPTION
- FUNCTIONAL DESCRIPTION
- SYSTEMS APPLICATIONS
- ABSOLUTE MAXIMUM RATINGS
- OPERATING RANGES
- DC CHARACTERISTICS
- SWITCHING CHARACTERISTICS
- KEY TO SWITCHING WAVEFORMS
- SWITCHING WAVEFORMS
- SWITCHING TEST CIRCUIT
- PHYSICAL DIMENSIONS
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
Publication# 20650
Rev: B Amendment/0
Issue Date: January 1998
Am79C984A
enhanced Integrated Multiport Repeater (eIMRTM)
DISTINCTIVE CHARACTERISTICS
s
Repeater functions comply with IEEE 802.3
Repeater Unit specifications
s
Four integral 10BASE-T transceivers with on-
chip filtering that eliminate the need for external
filter modules on the 10BASE-T transmit-data
(TXD) and receive-data (RXD) lines
s
One Reversible Attachment Unit Interface
(RAUITM) port that can be used either as a
standard IEEE-compliant AUI port for
connection to a Medium Attachment Unit (MAU),
or as a reversed port for direct connection to a
Media Access Controller (MAC)
s
Low cost suitable for non-managed multiport
repeater designs
s
Expandable to increase number of repeater
ports with support for up to seven eIMR devices
without the need for an external arbiter
s
All ports can be individually isolated
(partitioned) in response to excessive collision
conditions or fault conditions.
s
Full LED support for individual port status LEDs
and network utilization LEDs
s
Programmable extended distance mode on the
RXD lines, allowing connection to cables longer
than 100 meters
s
Twisted Pair Link Test capability conforming to
the 10BASE-T standard. The Link Test function
and the transmission of Link Test pulses can be
optionally disabled through the control port to
allow devices that do not implement the Link Test
function to work with the eIMR device.
s
Programmable option of automatic polarity
detection and correction permits automatic
recovery due to wiring errors
s
Full amplitude and timing regeneration for
retransmitted waveforms
s
CMOS device with a single +5-V supply
GENERAL DESCRIPTION
The enhanced Integrated Multiport Repeater (eIMR)
device is a VLSI integrated circuit that provides a sys-
tem-level solution to designing non-managed multiport
repeaters. The device integrates the repeater functions
specified in Section 9 of the IEEE 802.3 standard and
Twisted Pair Transceiver functions complying with the
10BASE-T standard.
The eIMR device provides four Twisted Pair (TP) ports
and one RAUI port for direct connection to a MAC. The
total number of ports per repeater unit can be in-
creased by connecting multiple eIMR devices through
their expansion ports, hence, minimizing the total cost
per repeater port.
The device is fabricated in CMOS technology and
requires a single +5-V supply.
P R E L I M I N A R Y
2
Am79C984A
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am79C984A
enhanced Integrated Multiport Repeater (eIMR)
TEMPERATURE RANGE
C = Commercial (0C to +70C)
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
PACKAGE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
K = 100-Pin Plastic Quad Flat Pack (PQR100)
Am79C984A
C
J
SPEED OPTION
Not Applicable
Valid Combinations
Am79C984A JC, KC\W
\W
P R E L I M I N A R Y
Am79C984A
3
BLOCK DIAGRAM
20650B-1
RX
MUX
Phase
Loc
k
Loop
FIFO
FIFO
CONTR
OL
Preamb
le
J
am Sequence
P
a
r
titioning
Link T
est
Timers
AU
I
Po
r
t
DI
CI
DO
TP
Po
r
t
0
RXD
TXD
RXD
TXD
Reset
Cloc
k
Gen
CLK
Expansion P
o
r
t
DA
T
JA
M
T
est
and
Control
Po
r
t
SI
SO
RST
SCLK
AMODE
20650A-1
RX
MUX
TX
MUX
eIMR Chip
Control
TP
Po
r
t
3
Manchester
Encoder
Manchester
Decoder
COL
AC
K
SELI
[1:0]
SELO
LED
Interf
ace
LD
A[4:0], LDB[4:0]
LDGA, LDGB
LDC[2:0]
A
CT[7:0]
P R E L I M I N A R Y
4
Am79C984A
RELATED AMD PRODUCTS
Part No.
Description
Am7990
Local Area Network Controller for Ethernet (LANCE)
Am7992B
Serial Interface Adapter (SIA)
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C90
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98
Twisted Pair Ethernet Transceiver (TPEX)
Am79C100
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C981
Integrated Multiport Repeater Plus (IMR+TM)
Am79C982
basic Integrated Multiport Repeater (bIMRTM)
Am79C987
Hardware Implemented Management Information Base
(HIMIBTM)
Am79C988
Quad Integrated Ethernet Transceiver (QuIETTM)
Am79C900
Integrated Local Area Communications Controller (ILACCTM)
Am79C940
Media Access Controller for Ethernet (MACETM)
Am79C960
PCnetTM-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961
PCnetTM-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft Plug n' Play Support)
Am79C961A
PCnetTM-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965
PCnetTM-32 Single-Chip 32-Bit Ethernet Controller
Am79C970
PCnetTM-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A
PCnetTM-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C983
Integrated Multiport Repeater 2 (IMR2TM)
Am79C985
enhanced Integrated Multiport Repeater Plus (eIMR+TM)
P R E L I M I N A R Y
Am79C984A
5
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
STANDARD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32
CONNECTION DIAGRAM (PL 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
CONNECTION DIAGRAM (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
PIN DESIGNATIONS (PL 084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
PIN DESIGNATIONS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Twisted Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Basic Repeater Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Repeater Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Signal Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Jabber Lockup Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Fragment Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Auto Partitioning/Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
TP Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Link Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Visual Status Monitoring (LED) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Network Activity Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
Internal Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
IMR+ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
Control Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49
Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50
Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50
SET (Write Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Chip Programmable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Alternate AUI Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Alternate TP Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
AUI Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
AUI Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
TP Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
TP Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Disable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Enable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Disable Link Pulse (Per TP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
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