PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21533
Rev: C Amendment/+5
Issue Date: October 18, 1999
Refer to AMD's Website (www.amd.com) for the latest information.
Am29DL16xC
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
-- Data can be continuously read from one bank while
executing erase/program functions in other bank
-- Zero latency between read and write operations
s
Multiple bank architectures
-- Three devices available with different bank sizes (refer
to Table 2)
s
Secured Silicon (SecSi) Sector: Extra 64 KByte sector
--
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
--
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
s
Zero Power Operation
-- Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
s
Package options
-- 48-ball FBGA
-- 56-pin SSOP
-- 48-pin TSOP
s
Top or bottom boot block
s
Manufactured on 0.32 m process technology
s
Compatible with JEDEC standards
-- Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
s
High performance
-- Access time as fast 70 ns
-- Program time: 7 s/word typical utilizing Accelerate function
s
Ultra low power consumption (typical values)
-- 2 mA active read current at 1 MHz
-- 10 mA active read current at 5 MHz
-- 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per sector
s
20 Year data retention at 125
C
-- Reliable operation for the life of the system
SOFTWARE FEATURES
s
Data Management Software (DMS)
-- AMD-supplied software manages data programming
and erasing, enabling EEPROM emulation
-- Eases sector erase limitations
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
-- Suspends erase operations to allow programming in
same bank
s
Data# Polling and Toggle Bits
-- Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
-- Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
-- Hardware method for detecting program or erase
cycle completion
s
Hardware reset pin (RESET#)
-- Hardware method of resetting the internal state
machine to reading array data
s
WP#/ACC input pin
-- Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
-- Acceleration (ACC) function accelerates program
timing
s
Sector protection
-- Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
-- Temporary Sector Unprotect allows changing data in
protected sectors in-system
2
Am29DL16xC
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29DL16xC family consists of 16 megabit, 3.0
volt-only flash memory devices, organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each.
Word mode data appears on DQ0DQ15; byte mode
data appears on DQ0DQ7. The device is designed to
be programmed in-system with the standard 3.0 volt
V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 80,
90, or 120 ns. The devices are offered in 56-pin SSOP,
48-pin TSOP, and 48-ball FBGA packages. Standard
control pins--chip enable (CE#), write enable (WE#),
and output enable (OE#)--control normal read and
write operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL16xC device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Three devices are available with the following
bank sizes:
Am29DL16xC Features
The Secured Silicon (SecSi) Sector is an extra 64
Kbit sector capable of being permanently locked by
AMD or customers. The SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is factory
locked, and set to a 0 if customer lockable. This way,
customer lockable parts can never be used to replace
a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD's ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s t e m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
Th e syste m can also place the device into th e
standby mode. Power consumption is greatly re-
duced in both modes.
Device
Bank 1
Bank 2
DL162
2 Mb
14 Mb
DL163
4 Mb
12 Mb
DL164
8 Mb
8 Mb
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