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Publication# 18514
Rev: D Amendment/0
Issue Date: October 1997
lan
TM
SC300
Highly Integrated, Low-Power, 32-Bit Microcontroller
DISTINCTIVE CHARACTERISTICS
n
Highly integrated, single-chip CPU and system
logic
Optimized for embedded PC applications
Combines 32 bit, x86 compatible, low-voltage
CPU with memory controller, PC/AT peripheral
controllers, real-time clock, and PLL clock gener-
ators
0.7 micron, low-voltage, CMOS process, fully
static
n
Enhanced Am386
SXLV CPU core
25 MHz or 33 MHz operating frequencies
3.3 V core, 3.3 V or 5 V memory and I/O
Low-power, fully static design for long battery life
System Management Mode (SMM) for power
management control
n
Integrated power management functions
Internal clock generators (using multiple Phase-
Locked Loops and one external 32-KHz crystal)
Supports CPU System Management Mode
(SMM)
Multiple operating modes: High Speed PLL, Low
Speed PLL, Doze, Sleep, Suspend, and Off. Fully
static design allows stopped clock.
Comprehensive control of system and peripheral
clocks
Five external power management control pins
Suspend refresh of DRAM array
Clock switching during ISA cycles
Low power consumption: 0.12 mW typical
Suspend mode power
Simultaneous multiple-voltage I/O pads operate
at either 3.3 V or 5 V. Core operates at 3.3 V for
minimum power consumption.
n
Integrated memory controller
Controls symmetrically addressable DRAM or
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit
DRAM or SRAM as main memory
Zero wait-state access with 70 ns, Page mode
DRAMs
Supports up to 16 Mbyte system memory
Supports up to 16 Mbyte of application ROM/
Flash, and 320 Kbyte direct ROM BIOS access.
Also supports shadow RAM
Fully PC/AT compatible
n
Integrated PC/AT-compatible peripheral logic
One programmable interval timer (fully 8254
compatible)
Two programmable interrupt controllers (8259A
compatible)
Two DMA controllers (8237A compatible)
Built-in real-time clock (146818A compatible),
with an additional 114 bytes of RAM
Internal Phase-Locked Loops (PLL) generate all
clocks from single 32.768 kHz crystal input
n
Bus configurations
16-bit data path
Optional bus configurations:
-- Internal LCD controller with subset ISA
-- 386 Local Bus mode with subset ISA
-- Maximum ISA Bus mode
Four programmable chip selects
Built-in 8042 chip select
n
Serial port controller (16450 UART compatible)
n
Bidirectional parallel port with EPP
n
Integrates two PCMCIA Version 2.1 slots
n
Integrated CGA-compatible LCD controller
Fully 6845 compatible
16 gray levels in Text mode; 2 or 4 levels in
Graphics mode
Supports the following LCD Panel Sizes:
-- 320 x 240 single scan (2 bpp)
-- 640 x 200 single/dual scan (1 bpp)
-- 480 x 320 single scan (1 bpp)
2
lanTMSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
GENERAL DESCRIPTION
The lanSC300 microcontroller is a highly integrated,
low-voltage, single-chip implementation of the
Am386SXLV microprocessor plus most of the addi-
tional logic needed for an AT-compatible personal com-
puter. It is ideal for embedded PC applications, such as
point-of-sale equipment, web appliances, industrial
controls, and communication equipment.
The lanSC300 microcontroller from AMD is part of the
growing lan family of mobile computing products,
which leverage existing AMD core modules. The
lanSC300 microcontroller demonstrates the feasibil-
ity of constructing highly integrated components built
from standard cores and getting these products to mar-
ket quickly.
The lanSC300 microcontroller does this by combining
an Am386SXLV low-voltage microprocessor core with
a memory control unit, a Power Management Unit
(PMU), and the bus control and peripheral control logic
of a PC/AT-compatible computer. For more information
a b o u t t h e A m 3 8 6 m i c r o p r o c e s s o r s , s e e t h e
Am386
SX/SXL/SXLV Data Sheet
, order #21020 and
the
Am386
DX/DXL Data Sheet
, order #21017.
For more information about the lanSC310 microcon-
troller, see the
lan
TM
SC300 Microcontroller Program-
mer's Reference Manual
, order #18470.
The lanSC300 microcontroller includes a memory
controller that supports up to 16 Mbyte of DRAM, Flash
or ROM; power management functions; a bus control-
ler that supports local or ISA bus; a serial port controller
that is 16450 UART compatible; a bidirectional EPP-
compliant parallel port; a 146818A-compatible
real-time clock; internal phase-locked loops for clock
generation; and standard PC logic chips (8259A,
8237A, and 8254).
The lanSC300 microcontroller's true static design
and low operating voltage enable battery-powered op-
eration and lower weight for embedded PC applica-
t i o n s . T h e i n t e r n a l c o r e o f t h e l a n S C 3 0 0
microcontroller operates at 3.3 V and the I/O pads
allow either 3.3 V or 5 V operation. Lowering typical op-
erating voltage from 5 V to 3.3 V can dramatically re-
duce power consumption.
Functionally, the lanSC300 microcontroller is a 100%
DOS/Windows-compatible, PC/AT-compatible com-
puter on a chip that is designed to furnish the customer
with a high-performance, low-power system solution,
providing state-of-the-art power management in a
small physical footprint.
The lanSC300 microcontroller is available in both 25-
and 33-MHz versions, in a 208-lead Plastic Shrink
Quad Flat Pack (QFP) (PQR package) and a 208-lead
Thin Quad Flat Pack (TQFP) (PQL package).
Note: Unless specified otherwise, the timings in this
data sheet are based on the 33-MHz version of the
lanSC300 microcontroller.
lanTMSC300 Microcontroller Data Sheet
3
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CUSTOMER SERVICE
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fices, international offices, and a customer training cen-
ter. Expert technical assistance is available from the
AMD worldwide staff of field application engineers and
factory support staff who can answer E86 family hard-
ware and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides a
toll-free number for direct access to our corporate ap-
plications hotline. Also available is the AMD World
Wide Web home page and FTP site, which provides the
latest E86 family product information.
Corporate Applications Hotline
(800) 222-9323
Toll-free for U.S. and Canada
44-(0) 1276-803-299
U.K. and Europe hotline
World Wide Web Home Page and FTP Site
To a c c e s s t h e A M D h o m e p a g e , g o t o h t t p : / /
www.amd.com.
Questions, requests, and input concerning AMD's
WWW pages can be sent via E-mail to webmas-
ter@amd.com.
To d o w n l o a d d o c u m e n t s a n d s o f t w a r e , f t p t o
ftp.amd.com and log on as anonymous using your
e-mail address as a password. Or via your web
browser, go to ftp://ftp.amd.com.
Documentation and Literature
Free E86 family information such as data books, user's
m a n u a l s , d a t a s h e e t s , a p p l i c a t i o n n o t e s , t h e
FusionE86 Partner Solutions Catalog, and other litera-
ture is available with a simple phone call. Internation-
ally, contact your local AMD sales office for complete
E86 family literature.
Literature Ordering
(800) 222-9323
Toll-free for U.S. and Canada
(512) 602-5651
Direct dial worldwide
4
lanTMSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
BLOCK DIAGRAM
ACIN, BLx, EXTSMI,
SUS/RES
M
U
X
MCEL, MCEH, VPP, REG
SLOT B
Power
Management
Control Unit
Bus Controller
Memory
Controller
Mapping
Registers
Parallel Port
Control
Serial Port
(16450)
PCMCIA
Interface
Interrupt
Controller
(2x8259)
Programmable
Interval Timer
(8254)
Real-Time Clock
(146818A)
Clock
Generators
Am386SXLV
DMA
Controller
(2x8237A-5)
A23A13, ADS, D/C,M/IO,
W/R, BHE, BLE, CPUCLK,
CPURST, CPURDY
LRDY, LDEV
RAS, CAS, MWE
PGP3PGP0
PPDWE, PPOEN
AFDT, STRB, SLCT, INIT
ACK, BUSY, ERROR, PE, SLCT
DTR, RTS, SOUT
CTS, DSR, DCD, SIN, RIN
MA11/SA12
MA0/SA23
MCEL, MCEH, VPP, REG
CD, RDY, WP, BVDx
}
SLOT A
CD, RDY, WP, BVDx
WAIT (common)
IRQx
PMCx
PD15PD0
PA23PA0
CONTROL
A20GATE, RC
8042CS, SYSCLK
IOR, IOW, MEMR,
MEMW, BALE
MCS16, IOCS16,
IOCHRDY, 0WS
DACKx, TC, AEN
DREQx
D15D0
SA12SA0
DSMD7DSMD0
LCD Interface
LCD
Controller
Local Bus
Controller
}
DSMA14DSMA0
LFX
X32OUT
X32IN
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