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Publication# 21028
Rev: B Amendment/0
Issue Date: December 1998
lanTMSC400 and lanSC410
Single-Chip, Low-Power,
PC/AT-Compatible Microcontrollers
DISTINCTIVE CHARACTERISTICS
lanTMSC400 and lanSC410
Microcontrollers
s
E86
TM
family of x86 embedded processors
Offers improved time-to-market, software
migration, and field-proven development tools
s
Highly integrated single-chip CPU with a complete
set of common peripherals
Accelerates time-to-market with simplified
hardware
Low-power 0.35-micron process technology
Single chip delivers smallest system form factor
33-MHz, 66-MHz, and 100-MHz operating
frequencies
s
Am486
CPU core
Robust Microsoft
Windows
compatible CPU
8-Kbyte write-back cache for enhanced
performance
Fully static design with System Management
Mode (SMM) for power savings
s
Comprehensive power management unit
Seven modes of operation allow fine-tuning of
power requirements for maximum battery life
Provides a superset of APM 1.2 features
s
Glueless burst-mode
ROM/Flash memory/SRAM interface
Reduces system cost by allowing mask ROM and
Flash memory at the same time with three ROM/
Flash memory/SRAM chip selects
s
Glueless DRAM controller
Allows mixed DRAM types on a per-bank basis to
reduce system cost
s
VESA Local (VL) bus and ISA bus interface
Reduces time-to-market with a wide variety of off-
the-shelf companion chips
s
Standard PC/AT system logic
(PICs, DMACs, timer, RTC)
DOS, ROM-DOS, Windows, and industry-
standard BIOS support
Leverages the benefits of desktop computing
environment at embedded price points
s
Bidirectional parallel port with Enhanced
Parallel Port (EPP) mode
s
16550-compatible UART
s
Infrared port for wireless communication
Standard and high-speed
s
Keyboard interface
Matrix keyboard support with up to 15 rows and 8
columns
SCP-emulation mode for PC/AT and XT
keyboard support
lanSC400 Microcontroller Only
The lanSC400 microcontroller includes the following
additional features designed specifically for mobile
computing applications. The lanSC410 microcontrol-
ler does not include these features.
s
Dual PC Card (PCMCIA Version 2.1) controller
supports 8- or 16-bit data bus
End-user (after-market) system expansion
ExCA-compliant, 82365-register set compatible
Leverages off-the-shelf card and socket services
Supports DMA transfers between I/O PC cards
and system DRAM
s
LCD graphics controller
Supports monochrome and 4-bit color Super
Twisted Nematic (STN) LCDs
Unified Memory Architecture (UMA) eliminates
separate video memory
2
lanTMSC400 and lanSC410 Microcontrollers Data Sheet
GENERAL DESCRIPTION
The lanTMSC400 and lanSC410 microcontrollers
are the among the latest in a series of E86TM family
microcontrollers, which integrate proven x86 CPU
cores with a comprehensive set of on-chip peripherals
in a 0.35-micron process.
The lanSC400 and lanSC410 microcontrollers
combine a 32-bit, low-voltage Am486 CPU with a
complete set of PC/AT-compatible peripherals, along
with the power management features required for
battery operation.
Leveraging the benefits of the x86 desktop computing
environment, the lanSC400 and lanSC410 microcon-
trollers integrate all of the common logic and I/O func-
tionality associated with a PC/AT computing system into
a single device, eliminating the need for multiple periph-
eral chips. Fully integrated PC/AT-compatible peripher-
als include two 8259A-compatible programmable
interrupt controllers (PICs), two 8237A-compatible DMA
controllers, an 8254-compatible timer, a 16550 UART,
an IrDA controller, VL-bus and ISA bus controllers, a
real-time clock (RTC), and Enhanced Parallel Port
(EPP) mode for the parallel port.
With its low-voltage Am486
CPU core and ultra-small
form factor, the lanSC400 microcontroller is highly op-
timized for mobile computing applications. The
lanSC410 microcontroller is targeted specifically for
embedded systems.
A feature comparison of the two microcontrollers is
shown in Table 1 on page 3.
The lanSC400 and lanSC410 microcontrollers use
the industry-standard 486 microprocessor instruction
set. All software written for the x86 architecture family
is compatible with the lanSC400 and lanSC410
microcontrollers.
The lanSC400 and lanSC410 microcontrollers are
based on a fully static design and include an advanced
power management unit. Operating voltages are
2.7 V3.3 V with 5-V-tolerant I/O pads. Orderable in
both 33-MHz, 66-MHz, and 100-MHz peak processor
speeds, the product is available in the ultra-small
292 ball grid array (BGA) package.
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid
co mbinations and to check on newly released
combinations.
33
A
C
TEMPERATURE RANGE
C = Commercial
For 33 and 66 MHz: T
CASE
= 0
C to +95
C
For 100 MHz: T
CASE
= 0
C to +85
C
I = Industrial
For 33 and 66 MHz, T
CASE
= 40
C to +95
C
PACKAGE TYPE
A = 292-pin BGA (Ball Grid Array)
SPEED OPTION
33 = 33 MHz
66 = 66 MHz
100 = 100 MHz
ELANSC400
DEVICE NUMBER/DESCRIPTION
lanSC400 microcontroller
lanSC410 microcontroller
Valid Combinations
ELANSC40033
AC, AI
ELANSC40066
ELANSC400100
AC
ELANSC41033
AC, AI
ELANSC41066
ELANSC410100
AC
lanTMSC400 and lanSC410 Microcontrollers Data Sheet
3
Table 1.
Product Comparison--lanSC400 and lanSC410 Microcontrollers
Feature
lanSC410
lanSC400
Core CPU
L1 Cache
System management mode (SMM)
Floating-point unit
Am486 CPU
8-Kbyte Write-Back
Yes
No
Am486 CPU
8-Kbyte Write-Back
Yes
No
Data Bus
16, 32 bit
16, 32 bit
ISA Interface
ISA bus mastering
8, 16 bit
No
8, 16 bit
No
VESA Local Bus
VL bus mastering
32 bit
No
32 bit
No
Power Management
Mode timers
Activity detection
SMI/NMI generation
Battery monitoring
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
On-Chip ROM Interface
Width
Size (total ROM space)
ROM chip selects
Burst-mode support
Support for SRAM as ROM address space
8, 16, 32 bit
3 x 64 Mbyte
3
Yes
Yes
8, 16, 32 bit
3 x 64 Mbyte
3
Yes
Yes
On-Chip DRAM Controller
Banks
Width
Size (total of all banks)
EDO support
Support for SRAM as main memory
4
16, 32 bit
64 Mbyte
Yes
ROM-mappable
4
16, 32 bit
64 Mbyte
Yes
ROM-mappable
Integrated PC/AT-Compatible Peripherals
Programmable timer (8254-compatible)
Real-time clock (146818A-compatible)
Port B and Port 92h I/O registers
Cascaded DMA Controllers (8237A)
Width
Total number of channels
External channels
Cascaded Interrupt Controllers (8259)
External IRQ signals
Yes
Yes
Yes
2
8, 16 bit
7
2
2
8
Yes
Yes
Yes
2
8, 16 bit
7
2
2
8
Bidirectional Parallel Port with EPP Mode
Yes
Yes
Serial Port (UART)
16550-compatible
16550-compatible
Keyboard Interface
Support for external 8042 SCP
XT interface
Matrix scanned with SCP emulation
Yes
Yes
Yes
Yes
Yes
Yes
General-Purpose Input/Output Signals
32
32
Infrared (IrDA) Port
Yes
Yes
PC Card Controller
Sockets
PCMCIA 2.1-compliant
82365-compatible
No
Yes
2
Yes
Yes
LCD Graphics Controller
Programmable clock frequency
Unified memory architecture (UMA)
No
Yes
Yes
Yes
JTAG Support
Yes
Yes
Pin Count and Package
292 BGA
292 BGA
V
CC
: CPU core
On-chip peripheral logic
I/O tolerance (designated pins)
2.73.3 V
3.3 V
5 V
2.73.3 V
3.3 V
5 V
Processor Clock Rate
33, 66, 100 MHz
33, 66, 100 MHz
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