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IF YOU HAVE QUESTIONS, WERE HERE TO HELP YOU.
Table of Contents
- List of Figures
- List of Tables
Introduction
- Élan’SC520 Microcontroller
- Purpose of this Manual
- Intended Audience
- Overview of this Manual
- Related Documents
- AMD Documentation
- Additional Information
- Documentation Conventions
- Table 0-1 Documentation Notation
Ch. 1 Configuration Register Overview
- 1.1 Memory-Mapped Configuration Region (MMCR) Registers
- Table 1-1 Memory-Mapped Configuration Region (MMCR) Registers (By Offset)
- 1.2 Direct-Mapped I/O Registers
- Table 1-2 Direct-Mapped I/O Registers
- 1.3 PCI Host Bridge Indexed Configuration Registers
- Table 1-3 PCI Indexed Registers
- 1.4 RTC and CMOS RAM Indexed Registers
- Table 1-4 Real-Time Clock Indexed Registers
Ch. 2 System Address Mapping Registers
- 2.1 Overview
- 2.2 Registers
Ch. 3 Reset Generation Registers
- 3.1 Overview
- 3.2 Registers
  - Table 3-1 Reset Generation MMCR Registers
  - Table 3-2 Reset Generation Direct-Mapped Registers
  - System Board Information (SYSINFO)
  - Reset Configuration (RESCFG)
  - Reset Status (RESSTA)
  - Table 3-3 Microcontroller Reset Sources
  - SCP Data Port (SCPDATA)
  - SCP Command Port (SCPCMD)
  - System Control Port A (SYSCTLA)
Ch. 4 Am5x86® CPU Registers
- 4.1 Overview
- 4.2 Registers
Ch. 5 System Arbitration Registers
- 5.1 Overview
- 5.2 Registers
Ch. 6 PCI Bus Host Bridge Registers
- 6.1 Overview
- 6.2 Registers
Ch. 7 SDRAM Controller Registers
- 7.1 Overview
- 7.2 Registers
  - Table 7-1 SDRAM Controller MMCR Registers
  - SDRAM Control (DRCCTL)
  - SDRAM Timing Control (DRCTMCTL)
  - SDRAM Bank Configuration (DRCCFG)
  - SDRAM Bank 0…3 Ending Address (DRCBENDADR)
  - ECC Control (ECCCTL)
  - ECC Status (ECCSTA)
  - ECC Check Bit Position (ECCCKBPOS)
  - ECC Check Code Test (ECCCKTEST)
  - Table 7-2 Example ECC Check Codes and Associated Data
  - ECC Single-Bit Error Address (ECCSBADD)
  - ECC Multi-Bit Error Address (ECCMBADD)
Ch. 8 Write Buffer and Read Buffer Register
- 8.1 Overview
- 8.2 Register
  - Table 8-1 Write Buffer and Read Buffer MMCR Register
  - SDRAM Buffer Control (DBCTL)
Ch. 9 ROM/Flash Controller Registers
- 9.1 Overview
- 9.2 Registers
Ch. 10 General-Purpose Bus Controller Registers
- 10.1 Overview
- 10.2 Registers
Ch. 11 GP DMA Controller Registers
- 11.1 Overview
- 11.2 Registers
Ch. 12 Programmable Interrupt Controller Registers
- 12.1 Overview
- 12.2 Registers
Ch. 13 Programmable Interval Timer Registers
- 13.1 Overview
- 13.2 Registers
Ch. 14 General-Purpose Timer Registers
- 14.1 Overview
- 14.2 Registers
Ch. 15 Software Timer Registers
- 15.1 Overview
- 15.2 Registers
Ch. 16 Watchdog Timer Registers
- 16.1 Overview
- 16.2 Registers
  - Table 16-1 Watchdog Timer MMCR Registers
  - Watchdog Timer Control (WDTMRCTL)
  - Table 16-2 Watchdog Timer Exponent Selections
  - Watchdog Timer Count Low (WDTMRCNTL)
  - Watchdog Timer Count High (WDTMRCNTH)
Ch. 17 Real-Time Clock Registers
- 17.1 Overview
- 17.2 Registers
Ch. 18 UART Serial Port Registers
- 18.1 Overview
- 18.2 Registers
Ch. 19 Synchronous Serial Interface Registers
- 19.1 Overview
- 19.2 Registers
  - Table 19-1 SSI MMCR Registers
  - SSI Control (SSICTL)
  - Table 19-2 SSI Clock Speed Selections
  - SSI Transmit (SSIXMIT)
  - SSI Command (SSICMD)
  - SSI Status (SSISTA)
  - SSI Receive (SSIRCV)
Ch. 20 Programmable Input/Output Registers
- 20.1 Overview
- 20.2 Registers
Index

Élan

SC520 Microcontroller

Order #22005B

The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-
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Trademarks

AMD, the AMD logo, and combinations thereof, AMDebug, E86, and Élan are trademarks, Am486 and Am5

86 are registered trademarks, and

FusionE86 is a service mark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

ÉlanTMSC520 Microcontroller Register Set Manual

iii

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Go to AMD's home page at www.amd.com and follow the Support link for the latest AMD
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In addition, mature development tools and applications for the x86 platform are widely
available in the general marketplace.

ÉlanTMSC520 Microcontroller Register Set Manual

ÉlanTMSC520 Microcontroller Register Set Manual

TABLE OF CONTENTS

PREFACE

INTRODUCTION

ÉlanTMSC520 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv
Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv

Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv
Overview of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

AMD Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii

CHAPTER 1

CONFIGURATION REGISTER OVERVIEW

1-1

1.1 Memory-Mapped Configuration Region (MMCR) Registers. . . . . . . . . . . . 1-1
1.2 Direct-Mapped I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3 PCI Host Bridge Indexed Configuration Registers . . . . . . . . . . . . . . . . . . 1-10
1.4 RTC and CMOS RAM Indexed Registers. . . . . . . . . . . . . . . . . . . . . . . . . 1-11

CHAPTER 2

SYSTEM ADDRESS MAPPING REGISTERS

2-1

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Address Decode Control (ADDDECCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Write-Protect Violation Status (WPVSTA) . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Programmable Address Region 0 (PAR0) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 1 (PAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 2 (PAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 3 (PAR3) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 4 (PAR4) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 5 (PAR5) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 6 (PAR6) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 7 (PAR7) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 8 (PAR8) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 9 (PAR9) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 10 (PAR10) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 11 (PAR11) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 12 (PAR12) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 13 (PAR13) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 14 (PAR14) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Programmable Address Region 15 (PAR15) . . . . . . . . . . . . . . . . . . . . . . . 2-5
Configuration Base Address (CBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

CHAPTER 3

RESET GENERATION REGISTERS

3-1

3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

System Board Information (SYSINFO). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Reset Configuration (RESCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Reset Status (RESSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
SCP Data Port (SCPDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
SCP Command Port (SCPCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
System Control Port A (SYSCTLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ELANSC520