FINAL
Publication# 21020
Rev: A Amendment/0
Issue Date: April 1997
DISTINCTIVE CHARACTERISTICS
s
Member of the E86TM CPU series
16-bit data bus
24-bit address bus
16-Mbyte address range
Long-term stable supply from AMD
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40-, 33- and 25-MHz operating speeds
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Ideal for embedded applications
True Static design for low-power applications
35 V operation (at 25 MHz)
Ideal for cost-sensitive designs
True DC (0 MHz) operation
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Industry Standard Architecture
Supports world's largest software base for x86
architectures
Wide range of chipsets and BIOS available
Fully compatible with all 386SX systems and
software
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System Management Mode (SMM) for system
and power management (Am386SXLV only)
System Management Interrupt (SMI) for power
management independent of processor
operating mode and operating system
SMI coupled with I/O instruction break feature
provides transparent power off and auto resume
of peripherals which may not be "power aware"
SMI is non-maskable and has higher priority
than Non-Maskable Interrupt (NMI)
Automatic save and restore of the
microprocessor state
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100-lead Plastic Quad Flat Pack (PQFP) package
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Extended temperature version available
GENERAL DESCRIPTION
The Am386SX/SXL/SXLV microprocessors are low-
cost, high-performance CPUs for embedded applica-
tions. Embedded customers benefit from using the
Am386 microprocessor in a number of ways.
The Am386SX/SXL/SXLV microprocessors provide
embedded customers access to very inexpensive pro-
cessors and the highest performance of any 386SX
available anywhere. The 16-bit data path allows for in-
expensive memory design. Full static operation, cou-
pled with 3-V supplies, benefit customers who desire
low-power designs. Standby Mode allows the
Am386SXL/SXLV microprocessors to be clocked
down to 0 MHz (DC) and retain full register contents. A
float pin places all outputs in a three-state mode to fa-
cilitate board test and debug.
Additionally, the Am386SXLV microprocessor comes
with System Management Mode (SMM) for system and
power management. SMI (System Management Inter-
rupt) is a non-maskable, higher priority interrupt than
NMI and has its own code space (1 Mbyte in Real
Mode and 16 Mbyte in Protected Mode). SMI can be
coupled with the I/O instruction break feature to imple-
ment transparent power management of peripherals.
SMM can be used by system designers to implement
system and power management code independent of
the operating system or the processor mode.
Since the Am386SX/SXL/SXLV microprocessors are
supported as an embedded product in the E86 family,
customers can rely on long-term supply of product, and
extended temperature products.
In addition, customers have access to the largest se-
lection of inexpensive development tools, compilers,
and chipsets. A large number of PC operating systems
and Real Time Operating Systems (RTOS) support the
Am386SX/SXL/SXLV microprocessors. This means
cheaper development costs, and improved time to mar-
ket.
The Am386SX/SXL/SXLV microprocessor is available
in a small footprint 100-pin Plastic Quad Flat Pack
(PQFP) package.
Am386
SX/SXL/SXLV
High-Performance, Low-Power, Embedded Microprocessors
2
Am386SX/SXL/SXLV Microprocessors Data Sheet
F I N A L
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
NG
SX
SPEED OPTION
PROCESSOR TYPE
SX
= SX Processor
SXL
= SX Processor with Static Clock Implementation
SXLV = SXL Processor with Low-Voltage and SMI
TEMPERATURE RANGE
NG=100-Lead Plastic Quad Flat Pack (PQB-100)
PROCESSOR FAMILY
PACKAGE TYPE
Am386 Family
40 = 40 MHz
33 = 33 MHz
25 = 25 MHz
80386
Blank = Commercial (T
CASE
= 0
C to +100
C)
I = Industrial (T
CASE
= 40
C to +100
C)
I
40
Valid Combinations
Valid Combinations lists configurations
planned to be supported in volume for this
device. Consult the local AMD sales office
to confirm availability of specific valid
combinations and to check on newly
released combinations.
Valid Combinations
NG80386 SX
25
33
40
SXL
25
33
SXLV
25
ING80386 SX
25
F I N A L
Am386SX/SXL/SXLV Microprocessors Data Sheet
3
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
True Static Operation
(Am386SXL/SXLV Only)
The Am386SXL/SXLV microprocessor incorporates a
true static design. Unlike dynamic circuit design, the
Am386SXL/SXLV device eliminates the minimum op-
erating frequency restriction. It may be clocked from its
maximum speed all the way down to 0 MHz (DC). Sys-
tem designers can use this feature to design portable
applications with long battery life.
Standby Mode (Am386SXL/SXLV Only)
The true static design of the Am386SXL/SXLV micro-
processor allows for a Standby Mode. At any operating
speed, the microprocessor will retain its state (i.e., the
contents of all its registers). By shutting off the clock
completely, the device enters Standby Mode. Since
power consumption is proportional to clock frequency,
operating power consumption is reduced as the fre-
quency is lowered. In Standby Mode, typical current
draw is reduced to less than 20 microamps at DC. Not
only does this feature save battery life, but it also sim-
plifies the design of power-conscious portable applica-
tions in the following ways.
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Eliminates the need for software in BIOS to save
and restore the contents of registers.
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Allows simpler circuitry to control stopping of the
clock since the system does not need to know
the state of the processor.
Lower Operating Icc
(Am386SXL/SXLV Only)
True static design also allows lower operating Icc when
operating at any speed.
Performance on Demand
(Am386SXL/SXLV Only)
The Am386SXL/SXLV microprocessor retains its state
at any speed from 0 MHz (DC) to its maximum operat-
ing speed. With this feature, system designers may
vary the operating speed of the system to extend the
battery life in portable systems.
Pipeline/
Bus Size
Control
Effective Address Bus
Effective Address Bus
Dedicated ALU Bus
Barrel
Shifter,
Adder
Multiply/
Divide
Register
File
Decode
and
Sequencing
Control
ROM
Instruction
Decoder
3-Decoded
Instruction
Queue
Prefetcher/
Limit
Checker
Limit and
Attribute
PLA
Descriptor
Registers
3-Input
Adder
Page
Cache
Adder
Request
Prioritizer
Address
Driver
Protection
Test Unit
ALU
Control
ALU
Control
Instruction
Instruction
Code
Stream
32
32
32
25
32
Segmentation Unit
Paging Unit
Bus Control
HOLD, INTR,
NMI, ERROR,
BUSY, RESET,
HLDA, FLT,
SMI*, IIBEN*
BHE, BLE,
A23-A1
M/IO, D/C,
W/R, LOCK,
ADS, NA,
READY,
SMIADS*,
SMIRDY*
D15-D0
* On Am386SXLV only
32 Bit
Control
Attribute
PLA
and
Prefetch
Predecode
MUX/
Trans-
ceivers
Status
Flags
16-Byte
Code
Queue
D
i
s
pl
ace
m
ent
Bu
s
Ph
ysical A
ddre
ss Bu
s
Co
ntro
l
C
o
d
e
Fe
tch/
Pag
e
Ta
bl
e
Fetch
Li
ne
ar
Ad
dr
ess
Bus
Internal Control Bus
32
4
Am386SX/SXL/SXLV Microprocessors Data Sheet
F I N A L
For example, the system could operate at low speeds
during inactivity or polling operations. However, upon
interrupt, the system clock can be increased up to its
maximum speed. After a user-defined time-out period,
the system can be returned to a low (or 0 MHz) operat-
ing speed without losing its state. This design maximiz-
es battery life while achieving optimal performance.
Benefits of Lower Operating Voltage
(Am386SXLV Only)
The Am386SXLV microprocessor has an operating
voltage range of 3.0 V to 5.5 V. Low voltage allows for
lower operating power consumption, longer battery life,
and/or smaller batteries for portable applications.
Because power is proportional to the square of the volt-
age, reduction of the supply voltage from 5.0 V to 3.3 V
reduces power consumption by 56%. This directly
translates to a doubling of battery life for portable appli-
cations. Lower power consumption can also be used to
reduce the size and weight of the battery. Thus, 3.3-V
designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and
provides a less hostile environment for board design.
Lower operating voltage also reduces electromagnetic
radiation noise and makes FCC approval easier to ob-
tain.
SMM--System Management Mode
(Am386SXLV Only)
The Am386SXLV microprocessor has a System Man-
agement Mode (SMM) for system and power manage-
ment. This mode consists of two features: System
Management Interrupt (SMI) and I/O instruction break.
SMI--System Management Interrupt
SMI is implemented by using special bus interface
pins. This interrupt method can be used to perform sys-
tem management functions such as power manage-
ment independent of processor operating mode (Real,
Protected, or Virtual 8086 modes).
SMI can also be invoked in software. This allows sys-
tem software to communicate with SMI power manage-
ment code. In addition, the UMOV instruction allows
data transfers between SMI and normal system mem-
ory spaces.
Activating the SMI pin invokes a sequence that saves
the operating state of the processor into a separate
SMM memory space, independent of the main system
memory. After the state is saved, the processor is
forced into Real mode and begins execution at address
FFFFF0h in the SMM memory space where a far jump
to the SMM code is executed. This Real mode code
can perform its system management function and then
resume execution of the normal system software by ex-
ecuting an RES3 instruction which will reload the saved
processor state and continue execution in the main
system memory space. See Figure 1 for a general flow-
chart of an SMM operation.
CPU Interface--Pin Functions
The CPU interface for SMM consists of three pins ded-
icated to the SMI function. One pin, SMI, is the interrupt
input. The other two pins, SMIADS and SMIRDY, pro-
vide the control signals necessary for the separate
SMM mode memory space.
SMI sampled
active (Low)
Current instruction
finishes execution,
normal ADS goes inactive
CPU saves state to sepa-
rate SMM memory space,
starting at address 60000h
CPU enters Real Mode,
starts code fetches at
location FFFFF0h in
SMM memory space
Real Mode SMM interrupt
handler code execution (af-
ter FAR JUMP)
Restore saved state from
60000h with RES3 (0F 07)
opcode sequence
Normal code
execution
resumes
16305C002
Figure 1. SMM Flow
F I N A L
Am386SX/SXL/SXLV Microprocessors Data Sheet
5
Description of SMM Operation
(Am386SXLV Only)
The execution of a System Management Interrupt has
four distinct phases: the initiation of the interrupt via
SMI, a processor state save, execution of the SMM in-
terrupt code, and a processor state restore (to resume
normal operation).
Interrupt Initiation
A System Management Interrupt is initiated by the driv-
ing of a synchronous, active Low pulse on the SMI pin
until the first SMIADS is asserted. This pulse period will
ensure recognition of the interrupt. The CPU drives the
SMI pin active after the completion of the current oper-
ation (active bus cycle, instruction execution, or both).
The active drive of the pin by the CPU is released at the
end of the interrupt routine following the last register
read of the saved state. The CPU drives SMI High for
two CLK2 cycles prior to releasing the drive of SMI.
An SMI cannot be masked off by the CPU, and it will al-
ways be recognized by the CPU, regardless of operat-
ing modes. This includes the Real, Protected, and Vir-
tual-8086 modes of the processor.
While the CPU is in SMM, a bus hold request via the
HOLD pin is granted. The HLDA pin goes active after
bus release and the SMIADS pin floats along with the
other pins that normally float during a bus hold cycle.
SMI does not float during a Bus Hold cycle.
Processor State Save
The first set of SMM bus transfer cycles after the CPU's
recognition of an active SMI is the processor saving its
state to an external RAM array in a separate address
space from main system memory. This is accom-
plished by using the SMIADS and SMIRDY pins for ini-
tiation and termination of bus cycles, instead of the
ADS and READY pins. The 24-bit addresses to which
the CPU saves its state are 60000h600CBh and
60100h60127h. These are fixed address locations for
each register saved.
To ensure valid operation, pipelining must be disabled
while the processor is in SMM. There are 114 data
transfer cycles.
SMI Code Execution
After the processor state is saved to the separate SMM
memory space, the execution of the SMM interrupt rou-
tine code begins. The processor enters Real mode,
sets most of the register values to "reset" values (those
values normally seen after a CPU reset), and begins
fetching code from address FFFFF0h in the separate
SMM memory space. Normally, the first thing the inter-
rupt routine code does is a FAR JUMP to the Real
mode entry point for the SMM interrupt routine, which
is also in SMM memory space.
Both INTR and NMI are disabled upon entry into SMM.
The SMM code can be located anywhere within the
1-Mbyte Real mode address space, except for where
the processor state is saved. I/O cycles, as a result of
the IN, OUT, INS, and OUTS instructions, will go to the
normal address space, utilizing the normal ADS and
READY bus interface signals. This facilitates power
management code manipulating system hardware reg-
isters as needed through the standard I/O subsystem;
a separate I/O space is not implemented.
Processor State Restore
(Resuming Normal Execution)
Returning to normal code execution in the main system
memory, including restoring the processor operating
mode, is accomplished by executing a special code se-
quence. This code invokes a restore CPU state opera-
tion that reloads the CPU registers from the saved data
in the RAM controlled by SMIADS and SMIRDY.
The ES:EDI register pair must point to the physical ad-
dress of the processor save state (6000h). In Real
mode the address is calculated as ES16 + EDI offset.
The saved state should not cross a 64K boundary. The
RES3 instruction (0F 07) should be executed to start
the restore state operation. After completion of the re-
store state operation, the SMI pin will be deactivated by
the CPU and normal code execution will continue at the
point where it left off before the SMI occurred. There
are 114 data transfer cycles in the restore operation.
Software Features (Am386SXLV Only)
Several features of the SMI function provide support for
special operations during the execution of the system's
software. These features involve the execution of re-
served opcodes to induce specific SMI-related opera-
tions.
Software SMI Generation
Besides hardware initiation of the SMI via the SMI pin,
there is also a software-induced SMI mechanism. Gen-
erating a soft SMI involves setting a control bit (Bit 12)
in the Debug Control Register (DR7) and executing an
SMI instruction (opcode F1h).
The functional sequence of the software-based SMI is
identical to the hardware-based SMI with the exception
that the SMI pin is not initially driven active by an exter-
nal source. Upon execution of a soft SMI opcode, the
SMI pin is driven active (Low) by the processor before
the save state operation begins.
Memory Transfers to Main System Memory
While executing an SMI routine, the interrupt code can
initiate memory data reads and writes to the main sys-
tem memory using the normal ADS and READY pins.
This initiation is accomplished by using reserved op-
codes that are special forms of the MOV instruction
(called UMOV). The UMOV opcodes can move byte,
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