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Publication Number 27631 Revision A Amendment 4 Issue Date May 13, 2004
ADVANCE
INFORMATION
S29GLxxxN MirrorBit
TM
Flash Family
S29GL512N, S29GL256N, S29GL128N
512 Megabit, 256 Megabit, and 128 Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
110 nm MirrorBit process technology
Datasheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- 3 volt read, erase, and program operations
Enhanced VersatileI/OTM control
-- All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on V
IO
input.
V
IO
range is 1.65 to V
CC
Manufactured on 110 nm MirrorBit process
technology
SecSiTM (Secured Silicon) Sector region
-- 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
-- May be programmed and locked at the factory or by
the customer
Flexible sector architecture
-- S29GL512N: Five hundred twelve 64 Kword (128
Kbyte) sectors
-- S29GL256N: Two hundred fifty-six 64 Kword (128
Kbyte) sectors
-- S29GL128N: One hundred twenty-eight 64 Kword
(128 Kbyte) sectors
Compatibility with JEDEC standards
-- Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles per sector typical
20-year data retention typical
Performance Characteristics
High performance
-- 80 ns access time (S29GL128N, S29GL256N),
90 ns access time (S29GL512N)
-- 8-word/16-byte page read buffer
-- 25 ns page read times
-- 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
-- 25 mA typical active read current;
-- 50 mA typical erase/program current
-- 1 A typical standby mode current
Package options
-- 56-pin TSOP
-- 64-ball Fortified BGA
Software & Hardware Features
Software features
-- Program Suspend & Resume: read other sectors
before programming operation is completed
-- Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
-- Data# polling & toggle bits provide status
-- Unlock Bypass Program command reduces overall
multiple-word or byte programming time
-- CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
-- Advanced Sector Protection
-- WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
-- Hardware reset input (RESET#) resets device
-- Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
2
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The devices have
a 16-bit wide data bus that can also function as an 8-bit wide data bus by using
the BYTE# input. The device can be programmed either in the host system or in
standard EPROM programmers.
Access times as fast as 80 ns (S29GL128N, S29GL256N) or 90 ns (S29GL512N)
are available. Note that each access time has a specific operating voltage range
(V
CC
) and an I/O voltage range (V
IO
), as specified in the
Product Selector Guide
and the
Ordering Information (512 Mb)
sections. The devices are offered in a 56-
pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a V
CC
input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/OTM (V
IO
) control allows the host system to set the
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the V
IO
pin. This allows the device to operate in a 1.8 V or 3 V system environ-
ment as required.
Hardware data protection measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at V
CC
. Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
4
A d v a n c e I n f o r m a t i o n
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
S29GL512N ..............................................................................................................6
S29GL256N .............................................................................................................6
S29GL128N ..............................................................................................................6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .8
Special Package Handling Instructions ............................................................9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
S29GL512N ......................................................................................................... 11
S29GL256N ........................................................................................................ 11
S29GL128N ........................................................................................................ 11
Ordering Information (512 Mb) . . . . . . . . . . . . . . . 12
Ordering Information (256 Mb) . . . . . . . . . . . . . . . 13
Ordering Information (128 Mb) . . . . . . . . . . . . . . . 14
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 15
Table 1. Device Bus Operations ........................................... 15
Word/Byte Configuration .................................................................................15
VersatileIO
TM
(V
IO
) Control ..............................................................................15
Requirements for Reading Array Data ......................................................... 16
Page Mode Read .............................................................................................. 16
Writing Commands/Command Sequences ................................................. 16
Write Buffer ......................................................................................................17
Accelerated Program Operation ................................................................17
Autoselect Functions ......................................................................................17
Standby Mode ........................................................................................................17
Automatic Sleep Mode .......................................................................................17
RESET#: Hardware Reset Pin ......................................................................... 18
Output Disable Mode ........................................................................................ 18
Table 2. Sector Address TableS29GL512N ........................... 18
Table 3. Sector Address TableS29GL256N ........................... 33
Table 4. Sector Address TableS29GL128N ........................... 40
Autoselect Mode ................................................................................................ 44
Table 5. Autoselect Codes, (High Voltage Method) ................ 45
Sector Protection ................................................................................................45
Persistent Sector Protection .......................................................................45
Password Sector Protection ........................................................................45
WP# Hardware Protection .........................................................................45
Selecting a Sector Protection Mode .........................................................45
Advanced Sector Protection .......................................................................... 46
Lock Register ....................................................................................................... 46
Table 6. Lock Register ........................................................ 47
Persistent Sector Protection ...........................................................................47
Dynamic Protection Bit (DYB) ...................................................................47
Persistent Protection Bit (PPB) ................................................................. 48
Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 49
Table 7. Sector Protection Schemes ..................................... 49
Persistent Protection Mode Lock Bit .......................................................... 49
Password Sector Protection ........................................................................... 50
Password and Password Protection Mode Lock Bit ............................... 50
64-bit Password ....................................................................................................51
Persistent Protection Bit Lock (PPB Lock Bit) ............................................51
SecSi (Secured Silicon) Sector Flash Memory Region ...............................51
Write Protect (WP#) ........................................................................................53
Hardware Data Protection ..............................................................................53
Low VCC Write Inhibit ................................................................................53
Write Pulse "Glitch" Protection ................................................................53
Logical Inhibit ...................................................................................................53
Power-Up Write Inhibit ................................................................................53
Common Flash Memory Interface (CFI) . . . . . . . 53
Table 9. System Interface String.......................................... 55
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 57
Reading Array Data ...........................................................................................58
Reset Command .................................................................................................58
Autoselect Command Sequence ...................................................................58
Enter SecSi Sector/Exit SecSi Sector Command Sequence ................... 59
Word Program Command Sequence .......................................................... 59
Unlock Bypass Command Sequence ........................................................60
Write Buffer Programming .........................................................................60
Accelerated Program .....................................................................................61
Figure 1. Write Buffer Programming Operation....................... 63
Figure 2. Program Operation ............................................... 64
Program Suspend/Program Resume Command Sequence ....................64
Figure 3. Program Suspend/Program Resume ........................ 65
Chip Erase Command Sequence ................................................................... 65
Sector Erase Command Sequence ................................................................66
Figure 4. Erase Operation ................................................... 67
Erase Suspend/Erase Resume Commands .................................................. 67
Lock Register Command Set Definitions ....................................................68
Password Protection Command Set Definitions ......................................68
Non-Volatile Sector Protection Command Set Definitions ..................70
Global Volatile Sector Protection Freeze Command Set ......................70
Volatile Sector Protection Command Set ................................................... 71
SecSi Sector Entry Command .......................................................................... 71
SecSi Sector Exit Command ........................................................................... 72
Command Definitions ........................................................................................73
Table 12. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x16 .........................................................................73
Table 13. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x8 ...........................................................................76
Write Operation Status ...................................................................................78
DQ7: Data# Polling ...........................................................................................78
Figure 5. Data# Polling Algorithm ........................................ 80
RY/BY#: Ready/Busy# .......................................................................................80
DQ6: Toggle Bit I ................................................................................................81
Figure 6. Toggle Bit Algorithm ............................................. 82
DQ2: Toggle Bit II ..............................................................................................82
Reading Toggle Bits DQ6/DQ2 ..................................................................... 83
DQ5: Exceeded Timing Limits ........................................................................ 83
DQ3: Sector Erase Timer ................................................................................ 83
DQ1: Write-to-Buffer Abort ...........................................................................84
Table 14. Write Operation Status .........................................84
Figure 7. Maximum Negative Overshoot Waveform................. 85
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 85
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 9. Test Setup........................................................... 87
Table 15. Test Specifications ...............................................87
Key to Switching Waveforms . . . . . . . . . . . . . . . . 87
Figure 10. Input Waveforms and
Measurement Levels........................................................... 87
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 88
Read-Only OperationsS29GL512N Only ..................................................88
Read-Only OperationsS29GL256N Only .................................................89
Read-Only OperationsS29GL128N Only ..................................................90
Figure 11. Read Operation Timings....................................... 91
Figure 12. Page Read Timings.............................................. 91
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
5
A d v a n c e I n f o r m a t i o n
Hardware Reset (RESET#) .............................................................................. 92
Figure 13. Reset Timings..................................................... 92
Erase and Program OperationsS29GL512N Only ...................................93
Erase and Program OperationsS29GL256N Only ................................. 94
Erase and Program OperationsS29GL128N Only ...................................95
Figure 14. Program Operation Timings .................................. 96
Figure 15. Accelerated Program Timing Diagram .................... 96
Figure 16. Chip/Sector Erase Operation Timings ..................... 97
Figure 17. Data# Polling Timings
(During Embedded Algorithms) ............................................ 98
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99
Figure 19. DQ2 vs. DQ6 ...................................................... 99
Alternate CE# Controlled Erase and Program Operations
S29GL512N Only ...............................................................................................100
Alternate CE# Controlled Erase and Program Operations
S29GL256N Only ................................................................................................101
Alternate CE# Controlled Erase and Program Operations
S29GL128N Only ...............................................................................................102
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................ 103
Erase And Programming Performance . . . . . . . 104
TSOP Pin and BGA Package Capacitance . . . . 104
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . .105
TS056--56-Pin Standard Thin Small Outline Package (TSOP) ............105
LAA064--64-Ball Fortified Ball Grid Array (FBGA) ..............................106
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 107
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