PRELIMINARY

This Data Sheet states Spansion's current technical specifications regarding the Products described herein. This
Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# S70GL256M00_00Rev: A
Amendment/0
Issue Date: September 8, 2004

S70GL256M00

256 Megabit (8 M x 32-Bit/16 M x 16-Bit) MirrorBit

TM 3.0

Volt-only Uniform Sector Flash Memory with Versatile I/O

Control

Distinctive Characteristics

ARCHITECTURAL ADVANTAGES
Single power supply operation

-- 3 volt read, erase, and program operations

VersatileI/O

control

-- Device generates data output voltages and tolerates

data input voltages on the CE# and DQ inputs/outputs
as determined by the voltage on the V

pin; operates

from 1.65 to 3.6 V

Manufactured on 0.23 µm MirrorBit

process

technology

SecSiTM (Secured Silicon) Sector region

-- 128-doubleword/256-word sector for permanent,

secure identification through an
8-doubleword/16-word random Electronic Serial
Number, accessible through a command sequence

-- May be programmed and locked at the factory or by

the customer

Flexible sector architecture

-- Two hundred fifty-six 32 Kdoubleword (64 Kword)

sectors

Compatibility with JEDEC standards

-- Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent
write protection

100,000 erase cycles typical per sector
20-year data retention typical

PERFORMANCE CHARACTERISTICS
High performance

-- 110 ns access time

-- 30 ns page read times

-- 0.5 s typical sector erase time

-- 15 µs typical write buffer doubleword programming

time: 16-doubleword/32-word write buffer reduces
overall programming time for multiple-word updates

-- 4-doubleword/8-word page read buffer

-- 16-doubleword/32-word write buffer

Low power consumption (typical values at 3.0 V, 5

MHz)

-- 26 mA typical active read current

-- 100 mA typical erase/program current

-- 2 µA typical standby mode current

Package options

-- 80-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES
Software features

-- Program Suspend & Resume: read other sectors

before programming operation is completed

-- Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

-- Data# polling & toggle bits provide status

-- Unlock Bypass Program command reduces overall

programming time

-- CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash
devices

Hardware features

-- Sector Group Protection: hardware-level method of

preventing write operations within a sector group

-- Temporary Sector Group Unprotect: V

-level method

of changing code in locked sector groups

-- WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
group regardless of sector group protection settings

-- Hardware reset input (RESET#) resets device

-- Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

GENERAL DESCRIPTION

The S70GL256M00 consists of two 128 Mbit, 3.0 volt
single power supply flash memory devices and is or-
ganized as 8,388,608 doublewords or 16,777,216
words. The device has a 32-bit wide data bus that can
also function as an 16-bit wide data bus by using the
WORD# input. The device can be programmed either
in the host system or in standard EPROM program-
mers.

An access time of 110 or 120 ns is available. Note that
each access time has a specific operating voltage
range (V

) as specified in the

Product Selector Guide

and the

Ordering Information

sections. The device is

offered in an 80-ball Fortified BGA package. Each de-
vice has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a V

input, a high-voltage accelerated program

(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.

The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.

The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14
(toggle) status bits or monitor the Ready/Busy#
(RY/BY#) outputs to determine whether the operation
is complete. To facilitate programming, an Unlock By-
pass mode reduces command sequence overhead by
requiring only two write cycles to program data instead
of four.

The VersatileI/OTM (V

) control allows the host sys-

tem to set the voltage levels that the device generates

and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V

pin.

Refer to the Ordering Information section for valid V

options.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro-
gramming equipment.

The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.

The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.

T h e d evice re d uce s p ow er co ns ump ti on i n th e
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.

The SecSi

TM (Secured Silicon) Sector provides a

128-doubleword/256-word area for code or data that
can be permanently protected. Once this sector is pro-
tected, no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.

Spansion MirrorBit

flash technology combines years

of Flash memory manufacturing experience to pro-
duce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via hot-hole assisted
erase. The data is programmed using hot electron in-
jection.

RELATED DOCUMENTS

For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see

www.amd.com

Flash Memory

Product Informa-

tion

MirrorBit

Flash Information

Technical Docu-

mentation.

The following is a partial list of documents

closely related to this product:

MirrorBitTM Flash Memory Write Buffer Programming
and Page Buffer Read

Implementing a Common Layout for Spansion Mirror-
Bit and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Block diagram . . . . . . . . . . . . . . . . 5

Special Package Handling Instructions .................................... 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

x16 Mode .................................................................................. 7
x32 Mode .................................................................................. 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ....................................................... 9

Word/Byte Configuration .......................................................... 9
VersatileIO

) Control ........................................................ 9

Requirements for Reading Array Data ................................... 10

Page Mode Read ............................................................................10

Writing Commands/Command Sequences ............................ 10

Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10

Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11

Table 2. Sector Address Table........................................................ 12

Autoselect Mode ..................................................................... 18

Table 3. Autoselect Codes, (High Voltage Method) ....................... 18

Sector Group Protection and Unprotection ............................. 19

Table 4. Sector Group Protection/Unprotection Address Table ..... 19

Write Protect (WP#) ................................................................ 20
Temporary Sector Group Unprotect ....................................... 20

Figure 1. Temporary Sector Group Unprotect Operation ................20
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21

SecSi (Secured Silicon) Sector Flash Memory Region .......... 22

Table 5. SecSi Sector Contents ...................................................... 22
Figure 3. SecSi Sector Protect Verify ..............................................23

Hardware Data Protection ...................................................... 23

Low VCC Write Inhibit .....................................................................23
Write Pulse "Glitch" Protection ........................................................23
Logical Inhibit ..................................................................................23
Power-Up Write Inhibit ....................................................................23

Common Flash Memory Interface (CFI) . . . . . . . 23

Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28
Doubleword/Word Program Command Sequence ................. 28

Unlock Bypass Command Sequence ..............................................28
Write Buffer Programming ...............................................................28
Accelerated Program ......................................................................29
Figure 4. Write Buffer Programming Operation ...............................30
Figure 5. Program Operation ..........................................................31

Program Suspend/Program Resume Command Sequence ... 31

Figure 6. Program Suspend/Program Resume ...............................32

Chip Erase Command Sequence ........................................... 32
Sector Erase Command Sequence ........................................ 32

Figure 7. Erase Operation .............................................................. 33

Erase Suspend/Erase Resume Commands ........................... 33
Command Definitions ............................................................. 34

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 36

DQ7 and DQ5: Data# Polling .................................................. 36

Figure 8. Data# Polling Algorithm .................................................. 36

RY/BY#: Ready/Busy# ............................................................ 37
DQ6 and DQ14: Toggle Bits I ................................................. 37

Figure 9. Toggle Bit Algorithm ........................................................ 38

DQ2 and DQ10: Toggle Bits II ................................................ 38
Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10 ............ 38
DQ5 and DQ13: Exceeded Timing Limits ............................... 39
DQ3 and DQ11: Sector Erase Timer ...................................... 39
DQ1: Write-to-Buffer Abort ..................................................... 40

Table 12. Write Operation Status................................................... 40
Figure 10. Maximum Negative Overshoot Waveform .................... 41
Figure 11. Maximum Positive Overshoot Waveform ...................... 41

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12. Test Setup ..................................................................... 43
Table 13. Test Specifications ......................................................... 43

Key to Switching Waveforms. . . . . . . . . . . . . . . . 43

Figure 13. Input Waveforms and
Measurement Levels ...................................................................... 43

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44

Read-Only Operations ............................................................ 44

Figure 14. Read Operation Timings ............................................... 44
Figure 15. Page Read Timings ...................................................... 45

Hardware Reset (RESET#) .................................................... 46

Figure 16. Reset Timings ............................................................... 46

Erase and Program Operations .............................................. 47

Figure 17. Program Operation Timings .......................................... 48
Figure 18. Accelerated Program Timing Diagram .......................... 48
Figure 19. Chip/Sector Erase Operation Timings .......................... 49
Figure 20. Data# Polling Timings (During Embedded Algorithms) . 50
Figure 21. Toggle Bit Timings (During Embedded Algorithms) ...... 51
Figure 22. DQ2 vs. DQ6 ................................................................. 51

Temporary Sector Unprotect .................................................. 52

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 52
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 53

Alternate CE# Controlled Erase and Program Operations ..... 54

Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ...............................................................................55

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 55
Erase And Programming Performance. . . . . . . . 56
TSOP Pin and BGA Package Capacitance . . . . . 56
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

LSB08080-Ball Fortified Ball Grid Array (Fortified BGA)
13 x 11 mm Package .............................................................. 57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the

register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.

Table 1.

Device Bus Operations

Legend: L = Logic Low = V

, H = Logic High = V

, V

= 11.512.5 V, V

= 11.512.5V, X = Don't Care, SA = Sector Address,

= Address In, D

= Data In, D

OUT

= Data Out

Notes:

1. Addresses are A22:A0 in doubleword mode; A22:A-1 in word mode. Sector addresses are A22:A15 in both modes.

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the

"Sector Group Protection and Unprotection" section.

3. If WP# = V

, the first or last sector group remains protected. If WP# = V

, the first or last sector will be protected or unprotected as

determined by the method described in "Write Protect (WP#)". All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)

4. D

or D

OUT

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

Word/Byte Configuration

The WORD# pin controls whether the device data I/O
pins operate in the word or doubleword configuration.
If the WORD# pin is set at V

, the device is in double-

word configuration, DQ31DQ0 are active and con-
trolled by CE# and OE#.

If the WORD# pin is set at V

, the device is in word

configuration, and only data I/O pins DQ15DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31DQ16 are tri-stated, and the DQ23 and

DQ31 pins are used as inputs for the LSB (A-1) ad-
dress function.

VersatileIO

) Control

The VersatileIO

) control allows the host system

to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V

. See Ordering Information

for V

options on this device.

Operation

CE#

OE#

WE#

RESET#

WP#

ACC

Addresses

(Note 1)

DQ15

DQ0

DQ31DQ16

WORD#

= V

WORD#

= V

Read

OUT

DQ31DQ16

= High-Z,

DQ31 &

DQ23= A-1

Write (Program/Erase)

(Note 3)

(Note 4) (Note 4)

Accelerated Program

(Note 3)

(Note 4) (Note 4)

Standby

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Group Protect
(Note 2)

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Sector Group Unprotect
(Note 2)

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

(Note 4)

Temporary Sector Group
Unprotect

(Note 4) (Note 4)

High-Z

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See "Reading Array Data" for more information. Refer
to the AC Read-Only Operations table for timing speci-
fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 doublewords/8 words. The appropriate
p a g e i s s e l e c t e d b y t h e h i g h e r a d d r e s s b i t s
A(max)A2. Address bits A1A0 in doubleword mode
(A1A-1 in word mode) determine the specific word
within a page. This is an asynchronous operation; the
microprocessor supplies the specific word location.

The random or initial page access is equal to t

ACC

and subsequent page read accesses (as long as

the locations specified by the microprocessor falls
within that page) is equivalent to t

PACC

. When CE# is

deasserted and reasserted for a subsequent access,
the access time is t

ACC

or t

. Fast page mode ac-

cesses are obtained by keeping the "read-page ad-
dresses" constant and changing the "intra-read page"
addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
"Doubleword/Word Program Command Sequence"
section has details on programming data to the device

using both standard and Unlock Bypass command se-
quences.

An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.

Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.

Write Buffer

Accelerated Program Operation

The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.

If the system asserts V

on this pin, the device auto-

matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to re-
duce the time required for program operations. The
system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Re-
moving V

from the WP#/ACC pin returns the device

to normal operation.

Note that the WP#/ACC pin must

not be at V

for operations other than accelerated

programming, or device damage may result. WP# has
an internal pullup; when unconnected, WP# is at V

Autoselect Functions

If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.

Standby Mode

When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

.) If CE# and RESET# are held at V

, but not within

± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-
quires standard access time (t

) for read access

when the device is in either of these standby modes,
before it is ready to read data.

If the device is deselected during erasure or program-
ming , the device draws active current until th e
operation is completed.

Refer to the DC Characteristics table for the standby
current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t

ACC

30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

, the

device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

±0.3 V, the device

draws CMOS standby current (I

CC4

). If RESET# is held

at V

but not within V

±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the device is

disabled. The output pins are placed in the high
impedance state.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Table 2.

Sector Address Table

Sector

A22A15

Sector Size

(Kwords/Kdoublewords)

16-bit

Address Range

(in hexadecimal)

32-bit

Address Range

(in hexadecimal)

SA0

64/32

00000000FFFF

000000007FFF

SA1

64/32

01000001FFFF

00800000FFFF

SA2

64/32

02000002FFFF

010000017FFF

SA3

64/32

03000003FFFF

01800001FFFF

SA4

64/32

04000004FFFF

020000027FFF

SA5

64/32

05000005FFFF

02800002FFFF

SA6

64/32

06000006FFFF

030000037FFF

SA7

64/32

07000007FFFF

03800003FFFF

SA8

64/32

08000008FFFF

040000047FFF

SA9

64/32

09000009FFFF

04800004FFFF

SA10

64/32

0A00000AFFFF

050000057FFF

SA11

64/32

0B00000BFFFF

05800005FFFF

SA12

64/32

0C00000CFFFF

060000067FFF

SA13

64/32

0D00000DFFFF

06800006FFFF

SA14

64/32

0E00000EFFFF

070000077FFF

SA15

64/32

0F00000FFFFF

07800007FFFF

SA16

64/32

10000010FFFF

080000087FFF

SA17

64/32

11000011FFFF

08800008FFFF

SA18

64/32

12000012FFFF

090000097FFF

SA19

64/32

13000013FFFF

09800009FFFF

SA20

64/32

14000014FFFF

0A00000A7FFF

SA21

64/32

15000015FFFF

0A80000AFFFF

SA22

64/32

16000016FFFF

0B00000B7FFF

SA23

64/32

17000017FFFF

0B80000BFFFF

SA24

64/32

18000018FFFF

0C00000C7FFF

SA25

64/32

19000019FFFF

0C80000CFFFF

SA26

64/32

1A00001AFFFF

0D00000D7FFF

SA27

64/32

1B00001BFFFF

0D80000DFFFF

SA28

64/32

1C00001CFFFF

0E00000E7FFF

SA29

64/32

1D00001DFFFF

0E80000EFFFF

SA30

64/32

1E00001EFFFF

0F00000F7FFF

SA31

64/32

1F00001FFFFF

0F80000FFFFF

SA32

64/32

020000020FFFF

100000107FFF

SA33

64/32

21000021FFFF

10800010FFFF

SA34

64/32

22000022FFFF

110000117FFF

SA35

64/32

23000023FFFF

11800011FFFF

SA36

64/32

24000024FFFF

120000127FFF

SA37

64/32

25000025FFFF

12800012FFFF

SA38

64/32

26000026FFFF

130000137FFF

SA39

64/32

27000027FFFF

13800013FFFF

SA40

64/32

28000028FFFF

140000147FFF

SA41

64/32

29000029FFFF

14800014FFFF

SA42

64/32

2A00002AFFFF

150000157FFF

SA43

64/32

2B00002BFFFF

15800015FFFF

SA44

64/32

2C00002CFFFF

160000167FFF

SA45

64/32

2D00002DFFFF

16800016FFFF

SA46

64/32

2E00002EFFFF

170000177FFF

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

SA47

64/32

2F00002FFFFF

17800017FFFF

SA48

64/32

30000030FFFF

180000187FFF

SA49

64/32

31000031FFFF

18800018FFFF

SA50

64/32

32000032FFFF

190000197FFF

SA51

64/32

33000033FFFF

19800019FFFF

SA52

64/32

34000034FFFF

1A00001A7FFF

SA53

64/32

35000035FFFF

1A80001AFFFF

SA54

64/32

36000036FFFF

1B00001B7FFF

SA55

64/32

37000037FFFF

1B80001BFFFF

SA56

64/32

38000038FFFF

1C00001C7FFF

SA57

64/32

39000039FFFF

1C80001CFFFF

SA58

64/32

3A00003AFFFF

1D00001D7FFF

SA59

64/32

3B00003BFFFF

1D80001DFFFF

SA60

64/32

3C00003CFFFF

1E00001E7FFF

SA61

64/32

3D00003DFFFF

1E80001EFFFF

SA62

64/32

3E00003EFFFF

1F00001F7FFF

SA63

64/32

3F00003FFFFF

1F80001FFFFF

SA64

64/32

40000040FFFF

200000207FFF

SA65

64/32

41000041FFFF

20800020FFFF

SA66

64/32

42000042FFFF

210000217FFF

SA67

64/32

43000043FFFF

21800021FFFF

SA68

64/32

44000044FFFF

220000227FFF

SA69

64/32

45000045FFFF

22800022FFFF

SA70

64/32

46000046FFFF

230000237FFF

SA71

64/32

47000047FFFF

23800023FFFF

SA72

64/32

48000048FFFF

240000247FFF

SA73

64/32

49000049FFFF

24800024FFFF

SA74

64/32

4A00004AFFFF

250000257FFF

SA75

64/32

4B00004BFFFF

25800025FFFF

SA76

64/32

4C00004CFFFF

260000267FFF

SA77

64/32

4D00004DFFFF

26800026FFFF

SA78

64/32

4E00004EFFFF

270000277FFF

SA79

64/32

4F00004FFFFF

27800027FFFF

SA80

64/32

50000050FFFF

280000287FFF

SA81

64/32

51000051FFFF

28800028FFFF

SA82

64/32

52000052FFFF

290000297FFF

SA83

64/32

53000053FFFF

29800029FFFF

SA84

64/32

54000054FFFF

2A00002A7FFF

SA85

64/32

55000055FFFF

2A80002AFFFF

SA86

64/32

56000056FFFF

2B00002B7FFF

SA87

64/32

57000057FFFF

2B80002BFFFF

SA88

64/32

58000058FFFF

2C00002C7FFF

SA89

64/32

59000059FFFF

2C80002CFFFF

SA90

64/32

5A00005AFFFF

2D00002D7FFF

SA91

64/32

5B00005BFFFF

2D80002DFFFF

SA92

64/32

5C00005CFFFF

2E00002E7FFF

SA93

64/32

5D00005DFFFF

2E80002EFFFF

SA94

64/32

5E00005EFFFF

2F00002F7FFF

Table 2.

Sector Address Table (Continued)

Sector

A22A15

Sector Size

(Kwords/Kdoublewords)

16-bit

Address Range

(in hexadecimal)

32-bit

Address Range

(in hexadecimal)

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

SA95

64/32

5F00005FFFFF

2F80002FFFFF

SA96

64/32

60000060FFFF

300000307FFF

SA97

64/32

61000061FFFF

30800030FFFF

SA98

64/32

62000062FFFF

310000317FFF

SA99

64/32

63000063FFFF

31800031FFFF

SA100

64/32

64000064FFFF

320000327FFF

SA101

64/32

65000065FFFF

32800032FFFF

SA102

64/32

66000066FFFF

330000337FFF

SA103

64/32

67000067FFFF

33800033FFFF

SA104

64/32

68000068FFFF

340000347FFF

SA105

64/32

69000069FFFF

34800034FFFF

SA106

64/32

6A00006AFFFF

350000357FFF

SA107

64/32

6B00006BFFFF

35800035FFFF

SA108

64/32

6C00006CFFFF

360000367FFF

SA109

64/32

6D00006DFFFF

36800036FFFF

SA110

64/32

6E00006EFFFF

370000377FFF

SA111

64/32

6F00006FFFFF

37800037FFFF

SA112

64/32

70000070FFFF

380000387FFF

SA113

64/32

71000071FFFF

38800038FFFF

SA114

64/32

72000072FFFF

390000397FFF

SA115

64/32

73000073FFFF

39800039FFFF

SA116

64/32

74000074FFFF

3A00003A7FFF

SA117

64/32

75000075FFFF

3A80003AFFFF

SA118

64/32

76000076FFFF

3B00003B7FFF

SA119

64/32

77000077FFFF

3B80003BFFFF

SA120

64/32

78000078FFFF

3C00003C7FFF

SA121

64/32

79000079FFFF

3C80003CFFFF

SA122

64/32

7A00007AFFFF

3D00003D7FFF

SA123

64/32

7B00007BFFFF

3D80003DFFFF

SA124

64/32

7C00007CFFFF

3E00003E7FFF

SA125

64/32

7D00007DFFFF

3E80003EFFFF

SA126

64/32

7E00007EFFFF

3F00003F7FFF

SA127

64/32

7F00007FFFFF

3F80003FFFFF

SA128

64/32

80000080FFFF

400000407FFF

SA129

64/32

81000081FFFF

40800040FFFF

SA130

64/32

82000082FFFF

410000417FFF

SA131

64/32

83000083FFFF

41800041FFFF

SA132

64/32

84000084FFFF

420000427FFF

SA133

64/32

85000085FFFF

42800042FFFF

SA134

64/32

86000086FFFF

430000437FFF

SA135

64/32

87000087FFFF

43800043FFFF

SA136

64/32

88000088FFFF

440000447FFF

SA137

64/32

89000089FFFF

44800044FFFF

SA138

64/32

8A00008AFFFF

450000457FFF

SA139

64/32

8B00008BFFFF

45800045FFFF

SA140

64/32

8C00008CFFFF

460000467FFF

SA141

64/32

8D00008DFFFF

46800046FFFF

SA142

64/32

8E00008EFFFF

470000477FFF

Table 2.

Sector Address Table (Continued)

Sector

A22A15

Sector Size

(Kwords/Kdoublewords)

16-bit

Address Range

(in hexadecimal)

32-bit

Address Range

(in hexadecimal)

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

SA143

64/32

8F00008FFFFF

47800047FFFF

SA144

64/32

90000090FFFF

480000487FFF

SA145

64/32

91000091FFFF

48800048FFFF

SA146

64/32

92000092FFFF

490000497FFF

SA147

64/32

93000093FFFF

49800049FFFF

SA148

64/32

94000094FFFF

4A00004A7FFF

SA149

64/32

95000095FFFF

4A80004AFFFF

SA150

64/32

96000096FFFF

4B00004B7FFF

SA151

64/32

97000097FFFF

4B80004BFFFF

SA152

64/32

98000098FFFF

4C00004C7FFF

SA153

64/32

99000099FFFF

4C80004CFFFF

SA154

64/32

9A00009AFFFF

4D00004D7FFF

SA155

64/32

9B00009BFFFF

4D80004DFFFF

SA156

64/32

9C00009CFFFF

4E00004E7FFF

SA157

64/32

9D00009DFFFF

4E80004EFFFF

SA158

64/32

9E00009EFFFF

4F00004F7FFF

SA159

64/32

9F00009FFFFF

4F80004FFFFF

SA160

64/32

A00000A0FFFF

500000507FFF

SA161

64/32

A10000A1FFFF

50800050FFFF

SA162

64/32

A20000A2FFFF

510000517FFF

SA163

64/32

A30000A3FFFF

51800051FFFF

SA164

64/32

A40000A4FFFF

520000527FFF

SA165

64/32

A50000A5FFFF

52800052FFFF

SA166

64/32

A60000A6FFFF

530000537FFF

SA167

64/32

A70000A7FFFF

53800053FFFF

SA168

64/32

A80000A8FFFF

540000547FFF

SA169

64/32

A90000A9FFFF

54800054FFFF

SA170

64/32

AA0000AAFFFF

550000557FFF

SA171

64/32

AB0000ABFFFF

55800055FFFF

SA172

64/32

AC0000ACFFFF

560000567FFF

SA173

64/32

AD0000ADFFFF

56800056FFFF

SA174

64/32

AE0000AEFFFF

570000577FFF

SA175

64/32

AF0000AFFFFF

57800057FFFF

SA176

64/32

B00000B0FFFF

580000587FFF

SA177

64/32

B10000B1FFFF

58800058FFFF

SA178

64/32

B20000B2FFFF

590000597FFF

SA179

64/32

B30000B3FFFF

59800059FFFF

SA180

64/32

B40000B4FFFF

5A00005A7FFF

SA181

64/32

B50000B5FFFF

5A80005AFFFF

SA182

64/32

B60000B6FFFF

5B00005B7FFF

SA183

64/32

B70000B7FFFF

5B80005BFFFF

SA184

64/32

B80000B8FFFF

5C00005C7FFF

SA185

64/32

B90000B9FFFF

5C80005CFFFF

SA186

64/32

BA0000BAFFFF

5D00005D7FFF

SA187

64/32

BB0000BBFFFF

5D80005DFFFF

SA188

64/32

BC0000BCFFFF

5E00005E7FFF

SA189

64/32

BD0000BDFFFF

5E80005EFFFF

SA190

64/32

BE0000BEFFFF

5F00005F7FFF

Table 2.

Sector Address Table (Continued)

Sector

A22A15

Sector Size

(Kwords/Kdoublewords)

16-bit

Address Range

(in hexadecimal)

32-bit

Address Range

(in hexadecimal)

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

SA191

64/32

BF0000BFFFFF

5F80005FFFFF

SA192

64/32

C00000C0FFFF

600000607FFF

SA193

64/32

C10000C1FFFF

60800060FFFF

SA194

64/32

C20000C2FFFF

610000617FFF

SA195

64/32

C30000C3FFFF

61800061FFFF

SA196

64/32

C40000C4FFFF

620000627FFF

SA197

64/32

C50000C5FFFF

62800062FFFF

SA198

64/32

C60000C6FFFF

630000637FFF

SA199

64/32

C70000C7FFFF

63800063FFFF

SA200

64/32

C80000C8FFFF

640000647FFF

SA201

64/32

C90000C9FFFF

64800064FFFF

SA202

64/32

CA0000CAFFFF

650000657FFF

SA203

64/32

CB0000CBFFFF

65800065FFFF

SA204

64/32

CC0000CCFFFF

660000667FFF

SA205

64/32

CD0000CDFFFF

66800066FFFF

SA206

64/32

CE0000CEFFFF

670000677FFF

SA207

64/32

CF0000CFFFFF

67800067FFFF

SA208

64/32

D00000D0FFFF

680000687FFF

SA209

64/32

D10000D1FFFF

68800068FFFF

SA210

64/32

D20000D2FFFF

690000697FFF

SA211

64/32

D30000D3FFFF

69800069FFFF

SA212

64/32

D40000D4FFFF

6A00006A7FFF

SA213

64/32

D50000D5FFFF

6A80006AFFFF

SA214

64/32

D60000D6FFFF

6B00006B7FFF

SA215

64/32

D70000D7FFFF

6B80006BFFFF

SA216

64/32

D80000D8FFFF

6C00006C7FFF

SA217

64/32

D90000D9FFFF

6C80006CFFFF

SA218

64/32

DA0000DAFFFF

6D00006D7FFF

SA219

64/32

DB0000DBFFFF

6D80006DFFFF

SA220

64/32

DC0000DCFFFF

6E00006E7FFF

SA221

64/32

DD0000DDFFFF

6E80006EFFFF

SA222

64/32

DE0000DEFFFF

6F00006F7FFF

SA223

64/32

DF0000DFFFFF

6F80006FFFFF

SA224

64/32

E00000E0FFFF

700000707FFF

SA225

64/32

E10000E1FFFF

70800070FFFF

SA226

64/32

E20000E2FFFF

710000717FFF

SA227

64/32

E30000E3FFFF

71800071FFFF

SA228

64/32

E40000E4FFFF

720000727FFF

SA229

64/32

E50000E5FFFF

72800072FFFF

SA230

64/32

E60000E6FFFF

730000737FFF

SA231

64/32

E70000E7FFFF

73800073FFFF

SA232

64/32

E80000E8FFFF

740000747FFF

SA233

64/32

E90000E9FFFF

74800074FFFF

SA234

64/32

EA0000EAFFFF

750000757FFF

SA235

64/32

EB0000EBFFFF

75800075FFFF

SA236

64/32

EC0000ECFFFF

760000767FFF

SA237

64/32

ED0000EDFFFF

76800076FFFF

SA238

64/32

EE0000EEFFFF

770000777FFF

Table 2.

Sector Address Table (Continued)

Sector

A22A15

Sector Size

(Kwords/Kdoublewords)

16-bit

Address Range

(in hexadecimal)

32-bit

Address Range

(in hexadecimal)

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Autoselect Mode

The autoselect mode provides manufacturer and de-
vice identification, and sector group protection verifica-
tion, through identifier codes output on DQ7DQ0.
This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. However, the autoselect codes can also be
accessed in-system through the command register.

When using programming equipment, the autoselect
mode requires V

on address pin A9. Address pins

A6, A3, A2, A1, and A0 must be as shown in Table 3.

In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain-
ing address bits that are don't care. When all neces-
sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables

and

. This

method does not require V

. Refer to the Autoselect

Command Sequence section for more information.

Table 3.

Autoselect Codes, (High Voltage Method)

Legend: L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don't care.

Description

CE#

OE#

WE#

A22

A15

A14

A10

DQ23 to DQ16

DQ7 to DQ0

WORD#

= V

WORD#

= V

Manufacturer ID:
Spansion

01h

i
ce

Cycle 1

7Eh

Cycle 2

12h

Cycle 3

00h

Sector Protection
Verification

01h (protected),

00h (unprotected)

SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector

98h (factory locked),

18h (not factory locked)

SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector

88h (factory locked),

08h (not factory locked)

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

Sector Group Protection and Unprotection

The hardware sector group protection feature disables
both program and erase operations in any sector
group. The hardware sector group unprotection fea-
ture re-enables both program and erase operations in
previously protected sector groups. Sector group pro-
tection/unprotection can be implemented via two
methods.

Sector group protection/unprotection requires V

the RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 24 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector group unprotect, all unpro-
tected sector group must first be protected prior to the
first sector group unprotect write cycle.

The device is shipped with all sector groups unpro-
tected. Spansion offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through Spansion's ExpressFlashTM Ser-
vice. Contact an Spansion representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.

Table 4.

Sector Group Protection/Unprotection

Address Table

Sector Group

A22A15

SA0

00000000

SA1

00000001

SA2

00000010

SA3

00000011

SA4SA7

000001xx

SA8SA11

000010xx

SA12SA15

000011xx

SA16SA19

000100xx

SA20SA23

000101xx

SA24SA27

000110xx

SA28SA31

000111xx

SA32SA35

001000xx

SA36SA39

001001xx

SA40SA43

001010xx

SA44SA47

001011xx

SA48SA51

001100xx

SA52SA55

001101xx

SA56SA59

001110xx

SA60SA63

001111xx

SA64SA67

010000xx

SA68SA71

010001xx

SA72SA75

010010xx

SA76SA79

010011xx

SA80SA83

010100xx

SA84SA87

010101xx

SA88SA91

010110xx

SA92SA95

010111xx

SA96SA99

011000xx

SA100SA103

011001xx

SA104SA107

011010xx

SA108SA111

011011xx

SA112SA115

011100xx

SA116SA119

011101xx

SA120SA123

011110xx

SA124SA127

011111xx

SA128SA131

100000xx

SA132SA135

100001xx

SA136SA139

100010xx

SA140SA143

100011xx

SA144SA147

100100xx

SA148SA151

100101xx

SA152SA155

100110xx

SA156SA159

100111xx

SA160SA163

101000xx

SA164SA167

101001xx

SA168SA171

101010xx

SA172SA175

101011xx

SA176SA179

101100xx

SA180SA183

101101xx

SA184SA187

101110xx

SA188SA191

101111xx

SA192SA195

110000xx

SA196SA199

110001xx

SA200SA203

110010xx

SA204SA207

110011xx

SA208SA211

110100xx

SA212SA215

110101xx

SA216SA219

110110xx

SA220SA223

110111xx

SA224SA227

111000xx

SA228SA231

111001xx

SA232SA235

111010xx

SA236SA239

111011xx

SA240SA243

111100xx

SA244SA247

111101xx

SA248SA251

111110xx

SA252

11111100

SA253

11111101

SA254

11111110

SA255

11111111

Sector Group

A22A15

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Write Protect (WP#)

The Write Protect function provides a hardware
method of protecting the first or last sector without
using V

. Write Protect is one of two functions pro-

vided by the WP#/ACC input.

If the system asserts V

on the WP#/ACC pin, the de-

vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in "Sector Group Protection and Unprotection".
Note that if WP#/ACC is at V

when the device is in

the standby mode, the maximum input load current is
increased. See the table in "DC Characteristics".

If the system asserts V

on the WP#/ACC pin, the de-

vice reverts to whether the first or last sector was pre-
viously set to be protected or unprotected using the
method described in "Sector Group Protection and
Unprotection".

Note that WP# has an internal pullup;

when unconnected, WP# is at V

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to V

. During this mode, for-

merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
V

is removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 1
shows the algorithm, and Figure 23 shows the timing
diagrams, for this feature.

Figure 1.

Temporary Sector Group

Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect Completed

(Note 2)

RESET# = V

(Note 1)

Notes:
1. All protected sector groups unprotected (If WP# = V

the first or last sector will remain protected).

2. All previously protected sector groups are protected

once again.

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

Figure 2.

In-System Sector Group Protect/Unprotect Algorithms

Sector Group Protect:

Write 60h to sector
group address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

group address

Wait 150 µs

Verify Sector Group

Protect: Write 40h

to sector group

address twith A6 = 0,

A1 = 1, A0 = 0

Read from

sector group address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1

µs

First Write

Cycle = 60h?

Data = 01h?

Remove V

from RESET#

Write reset

command

Sector Group

Protect complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Group Unprotect

Mode

Sector Group

Unprotect:

Write 60h to sector
group address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

group address

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector group

address with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = V

Wait 1

µs

Data = 00h?

Last sector

group

verified?

Remove V

from RESET#

Write reset

command

Sector Group

Unprotect complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Group Unprotect

Mode

All sector

groups

protected?

Yes

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

Set up

next sector group

address

Yes

Sector Group

Protect

Algorithm

Sector Group

Unprotect
Algorithm

First Write

Cycle = 60h?

Protect

another

sector group?

Reset

PLSCNT = 1

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

SecSi (Secured Silicon) Sector Flash
Memory Region

The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 doublewords/256
words in length, and uses SecSi Sector Indicator Bits
(DQ7 and DQ15) to indicate whether or not the SecSi
Sector is locked when shipped from the factory. These
bits are permanently set at the factory and cannot be
changed, which prevents cloning of a factory locked
part. This ensures the security of the ESN once the
product is shipped to the field.

Spansion offers the device with the SecSi Sector ei-
ther factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bits permanently set to a "1." The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a "0." Thus, the SecSi Sector Indi-
cator Bits prevent customer-lockable devices from
being used to replace devices that are factory locked.

The SecSi sector address space in this device is allo-
cated as follows:

Table 5.

SecSi Sector Contents

The system accesses the SecSi Sector through a
command sequence (see "Enter SecSi Sector/Exit
SecSi Sector Command Sequence"). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.

Note that the ACC

function and unlock bypass modes are not available
when the SecSi Sector is enabled.

Factory Locked: SecSi Sector Programmed and
Protected At the Factory

In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-doubleword/16-word random ESN at
addresses 000000h000007h.

Customers may opt to have their code programmed by
Spansion through the Spansion ExpressFlash service.
The devices are then shipped from Spansion's factory
with the SecSi Sector permanently locked. Contact an
Spansion representative for details on using Span-
sion's ExpressFlash service.

Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory

As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-doubleword/256 word SecSi
sector.

The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See To reduce power consumption
read Lower Byte only..

Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.

The SecSi Sector area can be protected using one of
the following procedures:

Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that

RESET# may be at either V

or V

. This

allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.

To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.

SecSi Sector

Address Range

Standard

Factory

Locked

ExpressFlash

Factory Locked

Customer

Lockable

x32

x16

000000h

000007h

000000h

00000Fh

ESN

ESN or

determined by

customer

Determined by

customer

000008h

00007Fh

000010h

0000FFh

Unavailable

Determined by

customer

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

Figure 3.

SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables

and

for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be

caused by spurious system level signals during V

power-up and power-down transitions, or from system
noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V

is greater than V

LKO

. The

system must provide the proper signals to the control
pins to prevent unintentional writes when V

greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
V

, CE# = V

or WE# = V

. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up,

the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 69. To terminate reading CFI data,
the system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 69. The
system must write the reset command to return the
device to reading array data.

For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an Spansion representative for copies of
these documents.

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1 ms

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

COMMAND DEFINITIONS

Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Tables

and

define the valid register

command sequences.

Writing incorrect address and

data values or writing them in the improper sequence
may place the device in an unknown state. A reset
command is then required to return the device to read-
ing array data.

All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
w h i c h t h e s y s t e m c a n r e a d d a t a f r o m a n y
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.

The system

must issue the reset command to return

the device to the read (or erase-suspend-read) mode if
DQ5 or DQ13 goes high during an active program or
erase operation, or if the device is in the autoselect
mode. See the next section, Reset Command, for
more information.

See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 14 shows the timing diagram.

Reset Command

Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don't cares for this command.

The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.

The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to

the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.

The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.

If DQ5 or DQ13 goes high during a program or erase
operation, writing the reset command returns the de-
vice to the read mode (or erase-suspend-read mode if
the device was in Erase Suspend).

Note that if DQ1 or DQ9 goes high during a Write
Buffer Programming operation, the system must write
the Write-to-Buffer-Abort Reset command sequence
to reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 11 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and re-
quires V

on address pin A9. The autoselect com-

mand sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.

The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:

A read cycle at address XX00h returns the manu-

facturer code.

Three read cycles at addresses 01h, 0Eh, and 0Fh

return the device code.

A read cycle to an address containing a sector ad-

dress (SA), and the address 02h on A7A0 in dou-
bleword mode retur ns 0101h if the sector is
protected, or 0000h if it is unprotected.

The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Enter SecSi Sector/Exit SecSi Sector
Command Sequence

The SecSi Sector region provides a secured data area
containing an 8-doubleword/16-word random Elec-
tronic Serial Number (ESN). The system can access
the SecSi Sector region by issuing the three-cycle
Enter SecSi Sector command sequence. The device
continues to access the SecSi Sector region until the
system issues the four-cycle Exit SecSi Sector com-
mand sequence. The Exit SecSi Sector command se-
quence returns the device to normal operation. Tables

and

show the address and data requirements for

both command sequences. See also "SecSi (Secured
Silicon) Sector Flash Memory Region" for further infor-
mation.

Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-
abled.

Doubleword/Word Program Command
Sequence

Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is

not required to provide further

controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables

and

show the

address and data requirements for the word program
command sequence.

When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 and DQ15 or DQ6 and DQ14. Refer to the Write
Operation Status section for information on these sta-
tus bits.

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.

Note that the SecSi

Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from "0" back to a "1." Attempting to do so may
cause the device to set DQ5 and/or DQ13 = 1, or
cause the DQ7 and/or DQ15, and DQ6 and/or DQ14
status bits to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0." Only erase operations can convert a "0" to a
"1."

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 2020h. The
device then enters the unlock bypass mode. A two-cy-
cle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0A0h; the second cycle contains the pro-
gram address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Tables

and

show the re-

quirements for the command sequence.

During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
9090h. The second cycle must contain the data 00h.
The device then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a
maximum of 16 doublewords/32 words in one pro-
gramming operation. This results in faster effective
programming time than the standard programming al-
gorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the
Write Buffer Load command written at the Sector Ad-
dress in which programming will occur. The fourth
cycle writes the sector address and the number of
word locations, minus one, to be programmed. For ex-
ample, if the system will program 6 unique address lo-
cations, then 0505h should be written to the device.
This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect
the Program Buffer to Flash command. The number of
locations to program cannot exceed the size of the
write buffer or the operation will abort.

The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits A23A4. All subsequent ad-
d r e s s / d a t a p a i r s m u s t f a l l w i t h i n t h e
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.

The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.

Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.

Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7 and DQ15, DQ6 and DQ14, DQ5
and DQ13, and DQ1 and DQ9 should be monitored to
determine the device status during Write Buffer Pro-
gramming.

The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.

The Write Buffer Programming Sequence can be
aborted in the following ways:

Load a value that is greater than the page buffer

size during the Number of Locations to Program
step.

Write to an address in a sector different than the

one specified during the Write-Buffer-Load com-
mand.

Write an Address/Data pair to a different

write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.

Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 and DQ9 = 1,
DQ7 and DQ15 = DATA# (for the last address location
loaded), DQ6 and DQ14 = toggle, and DQ5 and DQ13
=0. A Write-to-Buffer-Abort Reset command sequence
must be written to reset the device for the next opera-
tion. Note that the full 3-cycle Write-to-Buffer-Abort
Reset command sequence is required when using
Write-Buffer-Programming features in Unlock Bypass
mode.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from "0" back to a "1." Attempting to do so may
cause the device to set DQ5 and/or DQ13= 1, or
cause the DQ7 and/or DQ15 and DQ6 and/or DQ14
status bits to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0." Only erase operations can convert a "0" to a
"1."

Accelerated Program

The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V

on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation.

Note that

the WP#/ACC pin must not be at V

for operations

other than accelerated programming, or device dam-
age may result. WP# has an internal pullup; when un-
connected, WP# is at V

Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Figure 4.

Write Buffer Programming Operation

Write "Write to Buffer"

command and

Sector Address

Write number of addresses

to program minus 1(WC)

and Sector Address

Write program buffer to

flash sector address

Write first address/data

Write to a different

sector address

FAIL or ABORT

PASS

Read DQ7 - DQ0 at

Last Loaded Address

Read DQ7 - DQ0 with

address = Last Loaded

Address

Write next address/data pair

WC = WC - 1

WC = 0 ?

Part of "Write to Buffer"
Command Sequence

Yes

Abort Write to

Buffer Operation?

DQ7 = Data?

DQ5 = 1?

DQ1 = 1?

Write to buffer ABORTED.
Must write "Write-to-buffer

Abort Reset" command

sequence to return

to read mode.

Notes:
1.

When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.

DQ7 and DQ15 may change simultaneously with
DQ5 and DQ13. Therefore, DQ7 and DQ15
should be verified.

If this flowchart location was reached because
DQ5 and DQ13 = "1", then the device FAILED. If
this flowchart location was reached because
DQ1= "1", then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1 and DQ9 =1,
write the Write-Buffer-Programming-Abort-Reset
command. if DQ5 and DQ13 =1, write the Reset
command.

See Tables

and

for command sequences

required for write buffer programming.

(Note 3)

(Note 1)

(Note 2)

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

Figure 5.

Program Operation

Program Suspend/Program Resume
Command Sequence

The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 15
µs max (5 µs typical) and updates the status bits. Ad-
dresses are not required when writing the Program
Suspend command.

After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.

The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.

After the Program Resume command is written, the
device reverts to programming. The system can deter-
mine the status of the program operation using the
DQ7 and DQ15 or DQ6 and DQ14 status bits, just as
in the standard program operation. See Write Opera-
tion Status for more information.

The system must write the Program Resume com-
mand (address bits are don't care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Tables

and

for program command

sequence.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Figure 6.

Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables

and

show the address and data requirements for the

chip erase command sequence.

When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7 and DQ15, DQ6
and DQ14, or DQ2 and DQ10. Refer to the Write Op-
eration Status section for information on these status
bits.

Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.

Note that the

SecSi Sector, autoselect, and CFI functions are un-
available when an program operation is in progress.

Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 11 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.

The device does

not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.

Note that the SecSi Sector,

autoselect, and CFI functions are unavailable when an
erase operation is in progress.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend
Command Sequence

Command is also valid for
Erase-suspended-program
operations

Autoselect and SecSi Sector
read operations are also allowed

Data cannot be read from erase- or
program-suspended sectors

Write Program Resume
Command Sequence

Read data as

required

Done

reading?

Yes

Write address/data

XXXh/30h

Device reverts to
operation prior to

Program Suspend

Write address/data

XXXh/B0h

Wait 15 µs

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

The system can monitor DQ3 and DQ11 to determine
if the sector erase timer has timed out (See the section
on DQ3 and DQ11: Sector Erase Timer.). The time-out
begins from the rising edge of the final WE# pulse in
the command sequence.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7 and DQ15, DQ6 and DQ14, or DQ2 and DQ10 in
the erasing sector. Refer to the Write Operation Status
section for information on these status bits.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.

Erase Suspend/Erase Resume
Commands

The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.

When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.

After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device "erase sus-
pends" all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ15DQ0. The system
can use DQ7 and DQ15, or DQ6 and DQ14 and DQ2
and DQ10 together, to determine if a sector is actively
erasing or is erase-suspended. Refer to the Write Op-
eration Status section for information on these status
bits.

After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 and DQ15 or DQ6
and DQ14 status bits, just as in the standard word pro-
gram operation. Refer to the Write Operation Status
section for more information.

In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.

To resume the sector erase operation, the system
must write the Erase Resume command. Fur ther
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

Figure 7.

Erase Operation

Notes:
1. See Tables

and

for program command sequence.

2. See the section on DQ3 and DQ10 for information on

the sector erase timer.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Command Definitions

Table 10.

Command Definitions (x32 Mode, WORD# = V

)

Legend:
X = Don't care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
DWC = Doubleword Count. Number of write buffer locations to load
minus 1.

Notes:
1.

See Table 1 for description of bus operations.

All values are in hexadecimal.

Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.

Data bits DQ31DQ16 are don't care in command sequences,
except for RD, PD and DWC.

Unless otherwise noted, address bits A22A11 are don't cares.

No unlock or command cycles required when device is in read
mode.

The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 and/or DQ13
goes high while the device is providing status information.

The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ31DQ16 are don't care. See the Autoselect
Command Sequence section for more information.

The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 9898h for

factory locked and 1818h for not factory locked. If WP# protects
the lowest address sector, the data is 8888h for factory locked
and 0808h for not factor locked.

11. The total number of cycles in the command sequence is

determined by the number of doublewords written to the write
buffer. The maximum number of cycles in the command
sequence is 21.

12. The data is 0000h for an unprotected sector and 0101h for a

protected sector.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.

17. The Erase Resume command is valid only during the Erase

Suspend mode.

18. Command is valid when device is ready to read array data or when

device is in autoselect mode.

Command

Sequence

(Note 1)

l
e

Bus Cycles (Notes 25)

First

Second Third

Fourth

Fifth Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

XXX

F0F0

t
o

lec

t
(N

Manufacturer ID

555

AAAA

2AA

5555

555

9090

X00

00000101

Device ID (Note 9)

555

AAAA

2AA

5555

555

9090

X01

22227

E7E

X0E

22221

212

X0F

2222
0000

SecSi

Sector Factory Protect

(Note 10)

555

AAAA

2AA

5555

555

9090

X03

(Note 10)

Sector Group Protect Verify
(Note 12)

555

AAAA

2AA

5555

555

9090

(SA)X02

0000/010

Enter SecSi Sector Region

555

AAAA

2AA

5555

555

8888

Exit SecSi Sector Region

555

AAAA

2AA

5555

555

9090

XXX

0000

Program

555

AAAA

2AA

5555

555

A0A0

Write to Buffer (Note 11)

555

AAAA

2AA

5555

2525

DWC

WBL

Program Buffer to Flash

2929

Write to Buffer Abort Reset (Note 13)

555

AAAA

2AA

5555

555

F0F0

Unlock Bypass

555

AAAA

2AA

5555

555

2020

Unlock Bypass Program (Note 14)

XXX

A0A0

Unlock Bypass Reset (Note 15)

XXX

9090

XXX

0000

Chip Erase

555

AAAA

2AA

5555

555

8080

555

AAAA

2AA

5555

555

1010

Sector Erase

555

AAAA

2AA

5555

555

8080

555

AAAA

2AA

5555

3030

Program/Erase Suspend (Note 16)

XXX

B0B0

Program/Erase Resume (Note 17)

XXX

3030

CFI Query (Note 18)

9898

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

Table 11.

Command Definitions (x16 Mode, WORD# = V

)

SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.

Notes:
1.

See Table 1 for description of bus operations.

All values are in hexadecimal.

Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.

Data bits DQ31DQ15 are don't care in command sequences.

Unless otherwise noted, address bits A22A11 are don't cares.

No unlock or command cycles required when device is in read
mode.

The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 and/or
DQ13goes high while the device is providing status information.

The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ31DQ16 are don't care. See the Autoselect
Command Sequence section for more information.

The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 9898h for

factory locked and 1818h for not factory locked. If WP# protects
the lowest address sector, the data is 8888h for factory locked
and 0808h for not factor locked.

11. The total number of cycles in the command sequence is

determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 37.

12. The data is 0000h for an unprotected sector group and 0101h for

a protected sector group.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.

17. The Erase Resume command is valid only during the Erase

Suspend mode.

18. Command is valid when device is ready to read array data or when

device is in autoselect mode.

Command

Sequence

(Note 1)

l
e

Bus Cycles (Notes 25)

First

Second Third

Fourth

Fifth Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

XXX

F0F0

t
o

lec

t
(N

)

Manufacturer ID

AAA

AAAA

555

5555

AAA

9090

X00

0101

Device ID (Note 9)

AAA

AAAA

555

5555

AAA

9090

X02

7E7E

X1C

1212

X1E

0000

SecSi

Sector Factory Protect

(Note 10)

AAA

AAAA

555

5555

AAA

9090

X06

(Note 10)

Sector Group Protect Verify
(Note 12)

AAA

AAAA

555

5555

AAA

9090

(SA)X04

0000/010

Enter SecSi Sector Region

AAA

AAAA

555

5555

AAA

8888

Exit SecSi Sector Region

AAA

AAAA

555

5555

AAA

9090

XXX

0000

Program

AAA

AAAA

555

5555

AAA

A0A0

Write to Buffer (Note 11)

AAA

AAAA

555

5555

2525

WBL

Program Buffer to Flash

2929

Write to Buffer Abort Reset (Note 13)

AAA

AAAA

555

5555

AAA

F0F0

Unlock Bypass

AAA

AAAA

555

5555

AAA

2020

Unlock Bypass Program (Note 14)

XXX

A0A0

Unlock Bypass Reset (Note 15)

XXX

9090

XXX

0000

Chip Erase

AAA

AAAA

555

5555

AAA

8080

AAA

AAAA

555

5555

AAA

1010

Sector Erase

AAA

AAAA

555

5555

AAA

8080

AAA

AAAA

555

5555

3030

Program/Erase Suspend (Note 16)

XXX

B0B0

Program/Erase Resume (Note 17)

XXX

3030

CFI Query (Note 18)

9898

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the status of a
program or erase operation: DQ2 and DQ10, DQ3 and
DQ11, DQ5 and DQ13, DQ6 and DQ14, and DQ7 and
DQ15. Table 12 and the following subsections describe the
function of these bits. DQ7 and DQ15 and DQ6 and DQ14
each offer a method for determining whether a program or
erase operation is complete or in progress. The device
also provides a ha rdware-b ase d output sign al,
RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been com-
pleted.

DQ7 and DQ5: Data# Polling

The Data# Polling bit, DQ7 and DQ15, indicates to the host
system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out-
puts on DQ7 and DQ15 the complement of the datum pro-
grammed to DQ7 and DQ15. This DQ7 and DQ15 status
also applies to programming during Erase Suspend. When
the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7 and DQ15. The
system must provide the program address to read valid sta-
tus information on DQ7 and DQ15. If a program address
falls within a protected sector, Data# Polling on DQ7 and
DQ15 is active for approximately 1 µs, then the device re-
turns to the read mode.

During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7 and DQ15. When the Embed-
ded Erase algorithm is complete, or if the device en-
ters the Erase Suspend mode, Data# Polling produces
a "1" on DQ7 and DQ15. The system must provide an
address within any of the sectors selected for erasure
to read valid status information on DQ7 and DQ15.

After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 and DQ15 is active for approximately 100
µs, then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 and DQ15 at an address within a
protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program
or Erase operation, DQ7 and DQ15 may change asyn-
chronously with DQ6DQ0 and DQ14DQ8 while Out-
put Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid
data on DQ7 and DQ15. Depending on when the sys-
tem samples the DQ7 and DQ15 output, it may read
the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has
val i d d at a, th e d a ta o u tpu ts o n D Q 6 D Q 0 a n d
D Q 1 4 D Q 8 may b e s ti ll i nva lid . Va l id d a t a o n
DQ15DQ0 will appear on successive read cycles.

Table 12 shows the outputs for Data# Polling on DQ7
and DQ15. Figure 8 shows the Data# Polling algo-
rithm. Figure 20 in the AC Characteristics section
shows the Data# Polling timing diagram.

Figure 8.

Data# Polling Algorithm

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7DQ0

Addr = VA

Read DQ7DQ0

Addr = VA

DQ7 = Data?

START

Notes:
1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.

2. DQ7 and DQ15 should be rechecked even if DQ5

and/or DQ13 = "1" because DQ7 and DQ15 may
change simultaneously with DQ5 and DQ13.

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 12
shows the outputs for RY/BY#.

DQ6 and DQ14: Toggle Bits I

Toggle Bit I on DQ6 and DQ14indicates whether an
Embedded Program or Erase algorithm is in progress
or complete, or whether the device has entered the
Erase Suspend mode. Toggle Bit I may be read at any
address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.

During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 and DQ14 to toggle. The system may use either
OE# or CE# to control the read cycles. When the oper-
ation is complete, DQ6 and DQ14 stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 and DQ14 toggles
for approximately 100 µs, then returns to reading array data.
If not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and ig-
nores the selected sectors that are protected.

The system can use DQ6 and DQ14 and DQ2 and DQ10
together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress), DQ6
and DQ14 toggle. When the device enters the Erase Sus-
pend mode, DQ6 and DQ14 stop toggling. However, the
system must also use DQ2 and DQ10 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 and DQ15 (see the subsection on
DQ7 and DQ15: Data# Polling).

If a program address falls within a protected sector,
DQ6 and DQ14 toggle for approximately 1 µs after the
program command sequence is written, then returns
to reading array data.

DQ6 and DQ14 also toggle during the erase-sus-
pend-program mode, and stops toggling once the Em-
bedded Program algorithm is complete.

Table 12 shows the outputs for Toggle Bit I on DQ6
and DQ14. Figure 9 shows the toggle bit algorithm.
Figure 21 in the "AC Characteristics" section shows
the toggle bit timing diagrams. Figure 22 shows the dif-
ferences between DQ2 and DQ10 and DQ6 and DQ14
in graphical form. See also the subsection on DQ2 and
DQ10: Toggle Bits II.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

Figure 9.

Toggle Bit Algorithm

DQ2 and DQ10: Toggle Bits II

The "Toggle Bits II" on DQ2 and DQ10, when used
with DQ6 and DQ14, indicate whether a particular
sector is actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sector is
erase-suspended. Toggle Bits II are valid after the ris-
ing edge of the final WE# pulse in the command se-
quence.

DQ2 and DQ10 toggle when the system reads at ad-
dresses within those sectors that have been selected
for erasure. (The system may use either OE# or CE#
to control the read cycles.) But DQ2 and DQ10 cannot
distinguish whether the sector is actively erasing or is
erase-suspended. DQ6 and DQ14, by comparison, in-
dicate whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are re-
quired for sector and mode information. Refer to Table
12 to compare outputs for DQ2 and DQ10 and DQ6
and DQ14.

Figure 9 shows the toggle bit algorithm in flowchart
form, and the section "DQ2 and DQ10: Toggle Bits II"
ex p l a i n s t h e a l g o r i t h m . S e e a l so t h e RY /B Y # :
Ready/Busy# subsection. Figure 21 shows the toggle
bit timing diagram. Figure 22 shows the differences
between DQ2 and DQ10 and DQ6 and DQ14 in
graphical form.

Reading Toggle Bits DQ6 and DQ14/DQ2
and DQ10

Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bits sta-
tus, it must read DQ15DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bits are not toggling, the de-
vice has completed the program or erase operation.
The system can read array data on DQ15DQ0 on the
following read cycle.

However, if after the initial two read cycles, the system
determines that one of the toggle bits are still toggling,
the system also should note whether the value of DQ5
and DQ13 is high (see the section on DQ5 and DQ13).
If it is, the system should then deter mine again
whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 and/or DQ13
went high. If the toggle bits are no longer toggling, the
device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7DQ0

Toggle Bit

= Toggle?

Read DQ7DQ0

Twice

Read DQ7DQ0

Note: The system should recheck the toggle bit even if
DQ5 and DQ13= "1" because the toggle bit may stop
toggling as DQ5 and DQ13 changes to "1." See the
subsections on DQ6 and DQ14 and DQ2 and DQ10 for
more information.

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 and/or
DQ13 has not gone high. The system may continue to
monitor the toggle bits and DQ5 and DQ13 through
successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Figure 9).

DQ5 and DQ13: Exceeded Timing Limits

D Q 5 i nd ic ate s w he th er th e p ro gram , e ra se, o r
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 and DQ13
produce a "1," indicating that the program or erase cycle
was not successfully completed.

The device may output a "1" on DQ5 and/or DQ13 if
the system tries to program a "1" to a location that was
previously programmed to "0." Only an erase opera-
tion can change a "0" back to a "1." Under this con-
dition, the device halts the operation, and when the
timing limit has been exceeded, DQ5 and/or DQ13
produces a "1."

In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).

DQ3 and DQ11: Sector Erase Timer

After writing a sector erase command sequence, the
system may rea d DQ3 and DQ 11 to de ter min e
whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out period is com-
plete, DQ3 and DQ11 switch from a "0" to a "1." If the
time between additional sector erase commands from
the system can be assumed to be less than 50 µs, the
system need not monitor DQ3 and DQ11. See also the
Sector Erase Command Sequence section.

After the sector erase command is written, the system
should read the status of DQ7 and DQ15 (Data# Poll-
ing) or DQ6 and DQ14 (Toggle Bits I) to ensure that
the device has accepted the command sequence, and
then read DQ3 and DQ11. If DQ3 and DQ11 are "1,"
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 and DQ11 are
"0," the device will accept additional sector erase com-
mands. To ensure the command has been accepted,
the system software should check the status of DQ3
and DQ11 prior to and following each subsequent sec-
tor erase command. If DQ3 and DQ11 are high on the
second status check, the last command might not
have been accepted.

Table 12 shows the status of DQ3 and DQ11 relative
to the other status bits.

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 and DQ9
p r o d u c e a " 1 " . T h e s y s t e m m u s t i s s u e t h e

Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Programming section for more details.

Table 12.

Write Operation Status

Notes:
1. DQ5 and DQ13 switch to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 and DQ13 for more information.

2. DQ7 and DQ15 and DQ2 and DQ10 require a valid address when reading status information. Refer to the appropriate subsection

for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 and DQ9 switch to `1' when the device has aborted the write-to-buffer operation.

Status

DQ7/DQ15

(Note 2)

DQ6/DQ14

DQ5/

DA13

(Note 1)

DQ3/

DQ11

DQ2/DQ10

(Note 2)

DQ1/

DQ9

RY/BY#

Standard

Mode

Embedded Program Algorithm

DQ7/DA15#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

N/A

Program

Suspend

Mode

Program-

Suspend

Read

Program-Suspended
Sector

Invalid (not allowed)

Non-Program
Suspended Sector

Data

Erase

Suspend

Mode

Erase-

Suspend

Read

Erase-Suspended
Sector

No toggle

N/A

Toggle

N/A

Non-Erase
Suspended Sector

Data

Erase-Suspend-Program
(Embedded Program)

DQ7/DQ15#

Toggle

N/A

Write-to-

Buffer

Busy (Note 3)

DQ7/DQ15#

Toggle

N/A

Abort (Note 4)

DQ7/DQ15#

Toggle

N/A

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65°C to +150°C

Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V

A9, OE#, WP#/ACC, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.5 V

All other pins (Note 1) . . . . . . 0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V.

Dur in g vo ltage tran sitions, inpu t or I/O pins may
overshoot V

to 2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V

+0.5 V.

See Figure 10. During voltage transitions, input or I/O
pins may overshoot to V

+2.0 V for periods up to 20 ns.

See Figure 11.

2. Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is 0.5 V. During voltage transitions, A9, OE#,
WP#/ACC, and RESET# may overshoot V

to 2.0 V for

periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, WP#/ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Ex posure of the d evice to absolute m aximum rating
conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T

) . . . . . . . . . 40°C to +85°C

Supply Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.03.6 V

(Note 5)

. . . . . . . . . . . . . . . . . . . . . . . . . 1.653.6 V

4. Operating ranges define those limits between which the

functionality of the device is guaranteed.

5. See ordering information for valid V

combinations.

The I/Os will not operate at 3 V when V

= 1.8 V

20 ns

+0.8 V

0.5 V

20 ns

2.0 V

Figure 10.

Maximum Negative

Overshoot Waveform

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

Figure 11.

Maximum Positive

Overshoot Waveform

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

DC CHARACTERISTICS

CMOS Compatible

Notes:
1.

On the WP#/ACC pin only, the maximum input load current when
WP# = V

is ± 5.0 µA.

The I

current listed is typically less than 2 mA/MHz, with OE# at

Maximum I

specifications are tested with V

= V

max.

active while Embedded Erase or Embedded Program is in

progress.

Automatic sleep mode enables the low power mode when
addresses remain stable for t

ACC

+ 30 ns.

If V

< V

, maximum V

for CE# and DQ I/Os is 0.3 V

Maximum V

for these connections is V

+ 0.3 V

voltage requirements.

Not 100% tested.

Parameter

Symbol

Parameter Description

(Notes)

Test Conditions

Min

Typ

Max

Unit

Input Load Current (1)

= V

to V

= V

max

±2.0

µA

LIT

A9, ACC Input Load Current

= V

CC max

; A9 = 12.5 V

µA

Reset Leakage Current

= V

CC max

; RESET# = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

= V

CC max

±2.0

µA

CC1

Active Read Current (2, 3)

CE# = V

IL,

OE# = V

1 MHz

5 MHz

CC2

Initial Page Read Current (2, 3)

CE# = V

IL,

OE# = V

1 MHz

100

10 MHz

160

CC3

Intra-Page Read Current (2, 3)

CE# = V

IL,

OE# = V

10 MHz

33 MHz

CC4

Active Write Current (3, 4)

CE# = V

IL,

OE# = V

100

120

CC5

Standby Current (3)

CE#, RESET# = V

± 0.3 V, WP# = V

µA

CC6

Reset Current (3)

RESET# = V

± 0.3 V, WP# = V

µA

CC7

Automatic Sleep Mode (3, 5)

= V

± 0.3 V; V

= V

± 0.3 V,

WP# = V

µA

ACC

ACC Accelerated Program Current (3)

CE# = V

, OE# = V

ACC pin

120

IL1

Input Low Voltage 1 (6, 7)

0.5

0.8

IH1

Input High Voltage 1 (6, 7)

1.9

+ 0.5

IL2

Input Low Voltage 2 (6, 8)

0.5

0.3 x V

IH2

Input High Voltage 2 (6, 8)

1.9

+ 0.5

Voltage for ACC Program Acceleration

= 2.7 3.6 V

11.5

12.5

Voltage for Autoselect and Temporary
Sector Unprotect

= 2.7 3.6 V

11.5

12.5

OH1

Output High Voltage

= 2.0 mA, V

= V

CC min

= V

0.85 V

OH2

= 100 µA, V

= V

CC min

= V

0.4

LKO

Low V

Lock-Out Voltage (6)

2.3

2.5

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase and Program Operations

Notes:
1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

3. For 116 doublewords/132 words programmed.

4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation.

5. AC specifications listed are tested with V

= V

. Contact Spansion for information on AC operation when V

CC.

Parameter

Speed Options

JEDEC

Std.

Description

110R

120R

Unit

AVAV

Write Cycle Time (Note 1)

Min

110

120

AVWL

Address Setup Time

Min

ASO

Address Setup Time to OE# low during toggle bit polling

Min

WLAX

Address Hold Time

Min

AHT

Address Hold Time From CE# or OE# high
during toggle bit polling

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OEPH

Output Enable High during toggle bit polling

Min

GHWL

Read Recovery Time Before Write
(OE# High to WE# Low)

Min

ELWL

CE# Setup Time

Min

WHEH

CE# Hold Time

Min

WLWH

Write Pulse Width

Min

WHDL

WPH

Write Pulse Width High

Min

WHWH1

Write Buffer Program Operation (Notes 2, 3)

Typ

240

µs

Effective Write Buffer Program Operation
(Notes 2, 4)

Per Word

Typ

7.5

µs

Per Doubleword

Typ

µs

Accelerated Effective Write Buffer Program
Operation (Notes 2, 4)

Per Word

Typ

6.25

µs

Per Doubleword

Typ

12.5

µs

Single Doubleword/Word Program Operation
(Note 2)

Word

Typ

µs

Doubleword

Typ

µs

Accelerated Single Doubleword/Word
Programming Operation (Note 2)

Word

Typ

µs

Doubleword

Typ

µs

WHWH2

Sector Erase Operation (Note 2)

Typ

0.5

sec

VHH

Rise and Fall Time (Note 1)

Min

250

VCS

Setup Time (Note 1)

Min

µs

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Notes:
1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

3. For 116 doublewords/132 words programmed.

4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation.

5. AC specifications listed are tested with V

= V

. Contact Spansion for information on AC operation when V

Parameter

Speed Options

JEDEC

Std.

Description

110R

120R

Unit

AVAV

Write Cycle Time (Note 1)

Min

110

120

AVWL

Address Setup Time

Min

ELAX

Address Hold Time

Min

DVEH

Data Setup Time

Min

EHDX

Data Hold Time

Min

GHEL

Read Recovery Time Before Write
(OE# High to WE# Low)

Min

WLEL

WE# Setup Time

Min

EHWH

WE# Hold Time

Min

ELEH

CE# Pulse Width

Min

EHEL

CPH

CE# Pulse Width High

Min

WHWH1

Write Buffer Program Operation (Notes 2, 3)

Typ

240

µs

Effective Write Buffer Program Operation (Notes
2, 4)

Per Word

Typ

7.5

µs

Per Doubleword

Typ

µs

Effective Accelerated Write Buffer Program
Operation (Notes 2, 4)

Per Word

Typ

6.25

µs

Per Doubleword

Typ

12.5

µs

Single Doubleword/Word Program Operation
(Note 2)

Word

Typ

µs

Doubleword

Typ

µs

Accelerated Single Doubleword/Word
Programming Operation (Note 2)

Word

Typ

µs

Doubleword

Typ

µs

WHWH2

Sector Erase Operation (Note 2)

Typ

0.5

sec

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V

, 10,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 3.0 V, 100,000 cycles.

3. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation.

4. For 116 doublewords or 1-32 words programmed in a single write buffer programming operation.

5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables

10 and 11 for further information on command definitions.

TSOP PIN AND BGA PACKAGE CAPACITANCE

Notes:
1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.5

3.5

sec

Excludes 00h programming

prior to erasure (Note 5)

Chip Erase Time

128

256

sec

Single Doubleword/Word Program
Time (Note 3)

Word

600

µs

Excludes system level

overhead (Note 6)

Doubleword

600

µs

Accelerated Single Doubleword/
Word Program Time

Word

540

µs

Doubleword

540

µs

Total Write Buffer Program Time (Note 4)

240

1200

µs

Effective Write Buffer Program
Time (Note 3)

Per Word

7.5

µs

Per Doubleword

µs

Total Accelerated Write Buffer Program Time (Note 4)

200

1040

µs

Effective Write Buffer Accelerated
Program Time (Note 3)

Per Word

6.25

µs

Per Doubleword

12.5

µs

Chip Program Time

126

292

sec

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

= 0

BGA

TBD

OUT

Output Capacitance

OUT

= 0

BGA

TBD

IN2

Control Pin Capacitance

= 0

BGA

TBD

Parameter Description

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150°C

Years

125°C

Years

September 8, 2004

S70GL256M00

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

LSB08080-Ball Fortified Ball Grid Array (Fortified BGA)
13 x 11 mm Package

3265 \ 16-038.15a

PACKAGE

LSB 080

JEDEC

N/A

D x E

13.00 mm x 11.00 mm

PACKAGE

SYMBOL

MIN

NOM

MAX

NOTE

---

1.60

PROFILE

0.40

---

BALL HEIGHT

1.00

---

1.11

BODY THICKNESS

13.00 BSC.

BODY SIZE

11.00 BSC.

BODY SIZE

9.00 BSC.

MATRIX FOOTPRINT

7.00 BSC.

MATRIX FOOTPRINT

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

0.50

0.60

0.70

BALL DIAMETER

1.00 BSC.

BALL PITCH

1.00 BSC

BALL PITCH

SD / SE

0.50 BSC.

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

NOTES:

DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.

ALL DIMENSIONS ARE IN MILLIMETERS.

BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

e REPRESENTS THE SOLDER BALL GRID PITCH.

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.

N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

80X

0.20

(2X)

0.20

0.25 C

0.25 M C

M C

A B

0.10

TOP VIEW

SIDE VIEW

0.20

INDEX MARK

CORNER

PIN A1

BOTTOM VIEW

CORNER

PIN A1

S70GL256M00

September 8, 2004

P R E L I M I N A R Y

REVISION SUMMARY

Revision A (September 8, 2004)

Initial release.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.

Trademarks

Spansion, the Spansion logo, and combinations thereof are registered trademarks of Spansion LLC.

ExpressFlash is a trademark of Spansion LLC.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S70GL256M00FFIRB0

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S70GL256M00FFIRB0