Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.

2.26.02
IntWBY

ISO9001

FS6158

-01

Two-Way/Four Way Motherboard Clock Generator/Buffer IC

1.0 Features

Generates the Host and Memory clocks required for

2-way and 4-way multi-processor (MP) clock-
partitioned platforms, including:
M Six differential current-mode Host clock pairs
M Two 3.3V Memory Reference clocks
M 66.67MHz and 14.318MHz 3.3V Reference

clocks for the FS6159 device

M Three optional 33.3MHz 1.8V APIC clocks

Control of current-mode Host clocks via IREF current

programming pin and ISEL_0:1 current multiplier pins

Optional APIC clocks enabled via APICON input

(see Table 5 for Pins 21-23 configuration)

Host clock frequency selection via the SEL_A,

SEL_B, and SEL133/100# pins

Active-low PWR_DWN# signal allows one complete

clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLL, and disables outputs

Spread-spectrum modulation (-0.5% at 31.5kHz) of

Host, Memory, APIC, and 66MHz Reference clocks,
enabled via SS_EN# input

Supports test mode and tristate output control to fa-

cilitate board testing

Available in a 48-pin SSOP and TSSOP

Table 1: Clock Parameters

CLOCK

GROUP

PINS

SUPPLY

VOLTAGE

SUPPLY

GROUP

FREQ.

(MHz)

PHASE

SKEW

(MAX)

HOST_P

0°

HOST_N

3.3V

VDD_H

133.33
100.00

180°

100ps

Pair to

Pair

MREF_P

0°

MREF_N

3.3V

VDD_M

66.67
50.00

180°

66REF

3.3V

VDD_66

66.67

0°

14REF

3.3V

VDD_R

14.318

0°

APIC

(

optional

)

1.8V

VDD_A

33.33

0°

Figure 1: Block Diagram

Crystal

Oscillator

XOUT

XIN

PWR_DWN#

FS6158

66REF

adjust

IREF

14REF

VDD_R

VSS_R

ISEL_0:1

÷6

÷8

APIC_0:2

VDD_A

VSS_A

÷3

÷4

VSS_M

VDD_M

MREF_P
MREF_N

VDD_66

VSS_66

÷1

÷2

VSS_H

VDD_H

HOST_P1:6

HOST_N1:6

PLL

SEL133/100#

SS_EN#

SEL_A:B

APICON

Control

optional

Figure 2: Pin Configuration

14REF

VDD_R

VSS_R

XOUT

VSS_R

VSS

VSS / APICON

VDD_R

66REF

VSS_66

SEL133/100#

ISEL_0

ISEL_1

VSS_A

VDD

SEL_A / APIC_0

SEL_B / APIC_1

MREF_P

MREF_N

VSS_H

HOST_N1

VSS_H

HOST_P2

IREF

HOST_P6

HOST_N6

VSS_H

61
58
-
0
1

VDD_A

SS_EN# / APIC_2

HOST_P5

HOST_P1

VDD_H

VDD_I

XIN

VSS_M

VSS_I

HOST_N2

VDD_66

PWR_DWN#

VDD_H

HOST_N5

VDD_H

HOST_N4

HOST_P4

HOST_N3

HOST_P3

VDD_H

VDD_M

ir 1

air 2

air 3

air

4

air 5

air 6

2.26.02

ISO9001

FS6158-01

Two-Way/Four Way Motherboard Clock Generator/Buffer IC

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI

= Input with Internal Pull-Up; DI

= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active-low pin

PIN

TYPE

NAME

DESCRIPTION

SUPPLY

APICON

Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks

VDD_R

APIC_0

One of three optional APIC clocks, enabled or disabled by APICON

VDD_A

DIO

SEL_A

One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.

VDD_A,

VDD_H

APIC_1

One of three optional APIC clocks, enabled or disabled by APICON

VDD_A

DIO

SEL_B

One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.

VDD_A,

VDD_H

APIC_2

One of three optional APIC clocks, enabled or disabled by APICON

VDD_A

DIO

SS_EN#

Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input
levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.

VDD_A,

VDD_H

14REF

One 14.318MHz clock output, provided as a reference clock to the companion clock device

VDD_R

66REF

One 66.67MHz clock output, provided as a reference clock to the companion clock device

VDD_66

IREF

A fixed precision resistor from this pin to ground provides a reference current used for the
differential current-mode HOST clock outputs

VDD_I

17, 18

ISEL_0
ISEL_1

The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs

VDD_66

45, 44

HOST_P1
HOST_N1

Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1

VDD_H

42, 41

HOST_P2
HOST_N2

Host clock pair #2; one of six pairs of current-steering differential current-mode outputs

VDD_H

39, 38

HOST_P3
HOST_N3

Host clock pair #3; one of six pairs of current-steering differential current-mode outputs

VDD_H

36, 35

HOST_P4
HOST_N4

Host clock pair #4; one of six pairs of current-steering differential current-mode outputs

VDD_H

33, 32

HOST_P5
HOST_N5

Host clock pair #5; one of six pairs of current-steering differential current-mode outputs

VDD_H

30, 29

HOST_P6
HOST_N6

Host clock pair #6; one of six pairs of current-steering differential current-mode outputs

VDD_H

MREF_P

One clock in a pair of outputs provided as a reference clock to a memory clock driver

VDD_M

MREF_N

One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver

VDD_M

PWR_DWN#

Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.

VDD_I

SEL133/100# Selects 133MHz or 100MHz Host clock frequency

VDD_66

VDD

3.3V core power supply

VDD_A

1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23

VDD_66

3.3V power supply for 66REF clock output

28, 34, 40, 46

VDD_H

3.3V power supply for the differential HOST clock outputs

VDD_I

3.3V power supply for IREF current reference input

VDD_M

3.3V power supply for MREF clock outputs

3, 48

VDD_R

3.3V power supply for the 14REF clock output and the crystal oscillator

VSS

Core Ground

VSS_66

Ground for the 66REF clock output

VSS_A

Ground for the APIC clock outputs

31, 37, 43

VSS_H

Ground for the differential HOST clock outputs

VSS_I

Ground for IREF current reference input

VSS_M

Ground for the MREF clock outputs

1, 6

VSS_R

Ground for the 14REF clock output and the crystal oscillator

XIN

14.318MHz crystal oscillator input

VDD_R

XOUT

14.318MHz crystal oscillator output

VDD_R

2.26.02

ISO9001

FS6158

-01

Two-Way/Four Way Motherboard Clock Generator/Buffer IC

2.0 Programming Information

Table 3: Function/Clock Enable Configuration

CONTROL INPUTS

(2)

CLOCK OUTPUTS (MHz)

PWR_DWN#

SEL133/100#

SEL_A

SEL_B

HOST_P1:6

HOST_N1:6

MREF_P,

MREF_N

66REF

APIC_0:2

(

optional

)

14REF

100.00

50.00

66.67

33.33

14.318

100.00

low

(1)

low

(1)

low

(1)

low

(1)

reserved

tristate

133.33

66.67

33.33

14.318

reserved

XIN÷2

XIN÷4

XIN÷8

XIN

IREF

tristate

low

Certain clock outputs may be disabled through a combination of SEL_A, SEL_B, and SEL133/100# logic states as defined in Table 3. Enabled clocks will continue to run while disabled clocks
are stopped low. Note that if clocks are disabled while active, glitches may occur.

Table 4: Synthesis Error

CLOCK

TARGET

(MHz)

ACTUAL

(MHz)

DEVIATION

(ppm)

100.0000

99.9963

-36.657

HOST_P1:6,

HOST_N1:6

133.3333

133.3072

-195.924

50.0000

49.9982

-36.657

MREF_P,

MREF_N

66.6667

66.6536

-195.924

66REF

66.6667

66.6642

-36.657

APIC_0:2

33.3333

33.3321

-36.657

48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.

Spread spectrum is disabled

Table 5: APICON Control

APICON

FREQUENCY SELECT CONTROL / APIC CLOCKS

PIN 47

PIN 21

PIN 22

PIN 23

SEL_A Input

(LVTTL)

SEL_B Input

(LVTTL)

SS_EN# Input

(LVTTL)

APIC_0 Output /

SEL_A Latched

Input

APIC_1 Output /

SEL_B Latched

Input

APIC_2 Output /

SS_EN# Latched

Input

3.0 HOST Buffer Current Control

The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF

pin to ground (VSS), and

2) the multiplier factor determined by the logic setting of

the ISEL_0 and ISEL_1 pins.

3.1 Current

Reference

The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is

IREF

REF

VDD_I

3.2 Current

Scaling

The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.

2.26.02

ISO9001

FS6158-01

Two-Way/Four Way Motherboard Clock Generator/Buffer IC

Table 6: Current Multiplier

ISEL_0

ISEL_1

MULTPLIER

= 5

REF

= 6

REF

= 4

REF

= 7

REF

Figure 2: Current Reference Circuit

IREF

Reference

Current I

REF

Mirror
Current

Additional
Mirror
Current

HOST_N

ISEL_0:1

HOST_P

1.1V

VDD_I (3.3V)

Table 7: HOST Current Selection

PROGRAM

RESISTOR

IREF

REFERENCE

CURRENT

REF

CURRENT

MULTIPLIER

TRACE

IMPEDANCE

OUTPUT

VOLTAGE

0.71V

475

(1%)

2.32mA

= 5

REF

0.59V

0.85V

475

(1%)

2.32mA

= 6

REF

0.71V

0.56V

475

(1%)

2.32mA

= 4

REF

0.47V

0.99V

475

(1%)

2.32mA

= 7

REF

0.82V

0.75V

221

(1%)

5mA

= 5

REF

0.62V

0.90V

221

(1%)

5mA

= 6

REF

0.75V

0.60V

221

(1%)

5mA

= 4

REF

0.50V

1.05V

221

(1%)

5mA

= 7

REF

0.84V

NOTE: Shaded row indicates the Primary System Configuration

Table 8: HOST Buffer Clock Outputs

HIGH DRIVE CURRENT (mA)

AT PRIMARY SYSTEM CONFIGURATION

Output

Voltage (V)

MIN.

TYP.

MAX.

3.30

0.00

3.14

-3.03

-4.22

-5.76

2.97

-5.66

-7.68

-9.86

2.81

-7.87

-10.30

-11.85

2.64

-9.67

-11.91

-12.45

2.48

-11.05

-12.56

-12.84

2.31

-11.98

-12.85

-13.16

2.14

-12.52

-13.07

-13.45

1.98

-12.77

-13.26

-13.72

1.81

-12.91

-13.42

-13.96

1.65

-12.99

-13.54

-14.17

1.48

-13.04

-13.64

-14.36

1.32

-13.07

-13.70

-14.52

1.15

-13.08

-13.73

-14.64

0.99

-13.09

-13.75

-14.71

0.82

-13.11

-13.76

-14.74

0.66

-13.12

-13.78

-14.76

0.49

-13.13

-13.79

-14.78

0.33

-13.13

-13.80

-14.80

0.16

-13.14

-13.81

-14.82

0.00

-13.15

-13.82

-14.83

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

Output Voltage (V)

Out

put

rrent

(

)

30
50
90

Max VOH

Data in this table represents nominal characterization data only

2.26.02

ISO9001

FS6158

-01

Two-Way/Four Way Motherboard Clock Generator/Buffer IC

4.0 Power

Management

The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.

Table 9: Latency Table

LATENCY

SIGNAL

STATE

MIN.

MAX.

Output:

2 clocks

3 clocks

Power

OFF

Device:

14REF

clocks

14REF

clocks

PWR_
DWN#

Power

3ms

Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.

Figure 3: PWR_DWN# Timing

Any Clock

(output)

PWR_DWN#

Any Clock

(internal)

VCO

Crystal

Oscillator

After 14REF

output shuts off...

3ms until clock is valid

Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.

5.0 Dual Function I/O Pins

Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10k pull-down resistor to ground is required
for a logic low and a 10k pull-up resistor to the clock
output VDD is required for a logic high. The 10k resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.

Figure 4: I/O Pin Programming

Clock Trace

Termination

Resistor

Device Solder

Pads

Ground or

Power Via

10k

Programming

Resistor

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FS6158-01

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FS6158-01