I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc., reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
FS6370-01
FS6370-01
FS6370-01
FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
1.0 Features
Just-in-time customization of clock frequencies via
internal non-volatile 128-bit serial EEPROM
I
2
C
-bus serial interface
Three on-chip PLLs with programmable Reference
and Feedback Dividers
Four independently programmable muxes and post
dividers
Programmable power-down of all PLLs and output
clock drivers
Tristate outputs for board testing
One PLL and two mux/post-divider combinations
can be modified via SEL_CD input
5V to 3.3V operation
Accepts 5MHz to 27MHz crystal resonators
ROM-based device available for cost reduction mi-
gration path contact your AMI sales representative
for more information
2.0 Description
The FS6370 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of elec-
tronic systems. Three EEPROM-programmable phase-
locked loops (PLLs) driving four programmable muxes
and post dividers provide a high degree of flexibility.
An internal EEPROM permits just-in-time factory pro-
gramming of devices for end user requirements.
Figure 1: Pin Configuration
1
16
2
3
4
5
6
7
8
15
14
13
12
11
10
9
VSS
SEL_CD
PD/SCL
VSS
XIN
XOUT
OE/SDA
VDD
MODE
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
VDD
FS
63
70
16-pin (0.150") SOIC
Figure 2: Block Diagram
I
2
C-bus
Interface
EEPROM
Power Down
Control
Post
Divider C
Post
Divider B
FS6370
PD/SCL
OE/SDA
Post
Divider A
CLK_A
CLK_B
CLK_C
Reference
Oscillator
PLL A
PLL B
MODE
XOUT
XIN
Mux B
Mux C
PLL C
Post
Divider D
CLK_D
Mux D
Mux A
SEL_CD
2
FS6370-01
FS6370-01
FS6370-01
FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
P
VSS
Ground
2
DI
U
SEL_CD
Selects one of two programmed PLL C, Mux C/D, and Post Divider C/D combinations
3
DI
U
PD/SCL
Power-Down Input (Run Mode) or
Serial Interface Clock Input (Program Mode)
4
P
VSS
Ground
5
AI
XIN
Crystal Oscillator Feedback
6
AO
XOUT
Crystal Oscillator Drive
7
DI
U
O
OE/SDA
Output Enable Input (Run Mode) or
Serial Interface Data Input/Output (Program Mode)
8
P
VDD
Power Supply (5V to 3.3V)
9
DI
U
MODE
Selects either Program Mode (low) or Run Mode (high)
10
DO
CLK_D
D Clock Output
11
P
VSS
Ground
12
DO
CLK_C
C Clock Output
13
DO
CLK_B
B Clock Output
14
P
VDD
Power Supply (5V to 3.3V)
15
DO
CLK_A
A Clock Output
16
P
VDD
Power Supply (5V to 3.3V)
3.0 Functional Block Description
3.1
Phase Locked Loops
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired fre-
quency by a ratio of integers. This frequency multiplica-
tion is exact.
As shown in Figure 3, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), and a Feedback Divider.
During operation, the reference frequency (f
REF
), gener-
ated by the on-board crystal oscillator, is first reduced by
the Reference Divider. The divider value is often referred
to as the modulus, and is denoted as N
R
for the Refer-
ence Divider. The divided reference is fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the PLL. The output of the VCO
is fed back to the PFD through the Feedback Divider (the
modulus is denoted by N
F
) to close the loop.
Figure 3: PLL Block Diagram
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Loop
Filter
REFDIV[7:0]
FBKDIV[10:0]
LFTC
CP
f
REF
f
VCO
Voltage
Controlled
Oscillator
f
PD
3
FS6370-01
FS6370-01
FS6370-01
FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
=
R
F
REF
VCO
N
N
f
f
.
3.1.1 Reference
Divider
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
grammed for any modulus from 1 to 255 by programming
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.1.2 Feedback
Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight prescaler could have
been used in the Feedback Divider. Unfortunately, a di-
vide-by-eight would limit the effective modulus of the en-
tire feedback divider to multiples of eight. This limitation
would restrict the ability of the PLL to achieve a desired
input-frequency-to-output-frequency ratio without making
both the Reference and Feedback Divider values com-
paratively large. Generally, very large values are unde-
sirable as they degrade the bandwidth of the PLL, in-
creasing phase jitter and acquisition time.
To understand the operation of the feedback divider, refer
to Figure 4. The M-counter (with a modulus always equal
to M) is cascaded with the dual-modulus prescaler. The
A-counter controls the modulus of the prescaler. If the
value programmed into the A-counter is A, the prescaler
will be set to divide by N+1 for A prescaler outputs.
Thereafter, the prescaler divides by N until the M-counter
output resets the A-counter, and the cycle begins again.
Note that N=8, and A and M are binary numbers.
Figure 4: Feedback Divider
Dual
Modulus
Prescaler
A
Counter
M
Counter
f
VCO
f
PD
FBKDIV[10:3]
FBKDIV[2:0]
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and
the entire modulus of the feedback divider becomes M
N.
Next, suppose that the A-counter is programmed to a
one. This causes the prescaler to switch to a divide-by-
N+1 for its first divide cycle and then revert to a divide-by-
N. In effect, the A-counter absorbs (or "swallows") one
extra clock during the entire cycle of the Feedback Di-
vider. The overall modulus is now seen to be equal to
M
N+1.
This example can be extended to show that the Feed-
back Divider modulus is equal to M
N+A, where AM.
3.1.3 Feedback
Divider
Programming
For proper operation of the Feedback Divider, the A-
counter must be programmed only for values that are
less than or equal to the M-counter. Therefore, not all
divider moduli below 56 are available for use. This is
shown in Table 2.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
A-COUNTER: FBKDIV[2:0]
M-COUNTER:
FBKDIV[10:3]
000
001
010
011
100
101
110
111
00000001
8
9
-
-
-
-
-
-
00000010
16
17
18
-
-
-
-
-
00000011
24
25
26
27
-
-
-
-
00000100
32
33
34
35
36
-
-
-
00000101
40
41
42
43
44
45
-
-
00000110
48
49
50
51
52
53
54
-
00000111
56
57
58
59
60
61
62
63
FEEDBACK DIVIDER MODULUS
4
FS6370-01
FS6370-01
FS6370-01
FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
3.2
Post Divider Muxes
As shown in Figure 2, a mux in front of each post divider
stage can select from any one of the three PLL frequen-
cies or the reference frequency. The mux selection is
controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers
(Muxes C and D in Figure 2) can be altered without re-
programming by a logic-level input on the SEL_CD pin.
3.3 Post
Dividers
A post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
=
P
R
F
REF
CLK
N
N
N
f
f
1
where N
P
is the post divider modulus. The extra integer in
the denominator permits more flexibility in the program-
ming of the loop for many applications where frequencies
must be achieved exactly.
The modulus on two of the four post dividers (Post Divid-
ers C and D in Figure 2) can be altered without repro-
gramming by a logic level on the SEL_CD pin.
4.0 Device
Operation
The FS6370 has two modes of operation:
Program Mode
, during which either the EEPROM or
the FS6370 control registers can be programmed di-
rectly with the desired PLL settings, and
Run Mode
, where the PLL settings stored the
EEPROM are transferred to the FS6370 control reg-
isters on power-up, and the device then operates
based on those settings.
Note that the EEPROM locations are not physically the
same registers used to control the FS6370.
Direct access to either the EEPROM or the FS6370 con-
trol registers is achieved in Program Mode. The
EEPROM register contents are automatically transferred
to the FS6370 control registers in normal device opera-
tion (Run Mode).
4.1 MODE
Pin
The MODE pin controls the mode of operation. A logic-
low places the FS6370 in Program Mode. A logic-high
puts the device in Run Mode. A pull-up on this pin de-
faults the device into Run Mode.
Reprogramming of either the control registers or the
EEPROM is permitted at any time if the MODE pin is a
logic-low.
Note, however, that a logic-high state on the MODE pin is
latched so that only
one
transfer of EEPROM data to the
FS6370 control registers can occur. If a second transfer
of EEPROM data into the FS6370 is desired, power
(VDD) must be removed and reapplied to the device.
The MODE pin also controls the function of the PD/SCL
and OE/SDA pins. In Run Mode, these two pins function
as power-down (PD) and output enable (OE) controls. In
Program Mode, the pins function as the I
2
C interface for
clock (SCL) and data (SDA).
4.2 SEL_CD
Pin
The SEL_CD pin provides a way to alter the operation of
PLL C, Muxes C and D, and Post Dividers C and D with-
out having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a "C1" or "D1"
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with "C2" or "D2" notation, per
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.3 Oscillator
Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
must be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
rise and fall times, and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01F or
0.1F capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
5
FS6370-01
FS6370-01
FS6370-01
FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
EEPROM Programmable 3-PLL Clock Generator IC
5.0 Run
Mode
If the MODE pin is set to a logic-high, the device enters
the Run Mode. The high state is latched (see MODE Pin).
The FS6370 then copies the stored EEPROM data into
its control registers and begins normal operation based
on that data when the self-load is complete.
The self-load process takes about 89,000 clocks of the
crystal oscillator. During the self-load time, all clock out-
puts are held low. At a reference frequency of 27MHz,
the self-load takes about 3.3ms to complete.
If the EEPROM is empty (all zeros), the crystal reference
frequency provides the clock for all four outputs.
No external programming access to the FS6370 is possi-
ble in Run Mode. The dual-function PD/SCL and OE/SDA
pins become a power-down (PD) and output enable (OE)
control, respectively.
5.1
Power-Down and Output Enable
A logic-high on the PD/SCL pin powers down only those
portions of the FS6370 which have their respective
power-down control bits enabled. Note that the PD/SCL
pin has an internal pull-up.
When a Post Divider is powered down, the associated
output driver is forced low. When all PLLs and Post Di-
viders are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE/SDA pin tristates all output clocks.
Note that this pin has an internal pull-up.
6.0 Program
Mode
If the MODE pin is logic-low, the device enters the Pro-
gram Mode. All internal registers are cleared to zero, de-
livering the crystal frequency to all outputs. The device
allows programming of either the internal 128-bit
EEPROM or the on-chip control registers via I
2
C control
over the PD/SCL and OE/SDA pins. The EEPROM and
the FS6370 act as two separate parallel devices on the
same on-chip I
2
C-bus. Choosing either the EEPROM or
the device control registers is done via the I
2
C device
address.
The dual-function PD/SCL and OE/SDA pins become the
serial data I/O (SDA) and serial clock input (SCL) for
normal I
2
C communications. Note that power-down and
output enable control via the PD/SCL and OE/SDA pins
is not available.
6.1 EEPROM
Programming
Data must be loaded into the EEPROM in a most-
significant-bit (MSB) to least-significant-bit (LSB) order.
The register map of the EEPROM is noted in Table 3.
The device address of the EEPROM is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
X
X
X
6.1.1 Write
Operation
The EEPROM can
only
be written to with the Random
Register Write Procedure (see Page 8). The procedure
consists of the device address, the register address, a
R/W bit, and one byte of data.
Following the STOP condition, the EEPROM initiates its
internally timed 4ms write cycle, and commits the data
byte to memory. No acknowledge signals are generated
during the EEPROM internal write cycle.
If a stop bit is transmitted before the entire write com-
mand sequence is complete, then the command is
aborted and no data is written to memory.
If more than eight bits are transmitted before the stop bit
is sent, then the EEPROM will clear the previously loaded
data byte and will begin loading the data buffer again.
6.1.2 Acknowledge
Polling
The EEPROM does not acknowledge while it internally
commits data to memory. This feature can be used to
increase data throughput by determining when the inter-
nal write cycle is complete.
The process is to initiate the Random Register Write Pro-
cedure with a START condition, the EEPROM device
address, and the write command bit (R/W=0). If the
EEPROM has completed its internal 4ms write cycle, the
EEPROM will acknowledge on the next clock, and the
write command can continue.
If the EEPROM has not completed the internal 4ms write
cycle, the Random Register Write Procedure must be
restarted by sending the START condition, device ad-
dress, and R/W bit. This sequence must be repeated until
the EEPROM acknowledges.
6.1.3 Read
Operation
The EEPROM supports both the Random Register Read
Procedure and the Sequential Register Read Procedure
(both are outlined on Page 8).
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