A29002/A290021 Series

256K X 8 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Features

5.0V

10% for read and write operations

Access times:

- 55/70/90/120/150 (max.)

Current:

- 20 mA typical active read current
- 30 mA typical program/erase current
- 1

A typical CMOS standby

Flexible sector architecture

16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector

Top or bottom boot block configurations available

Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated
sectors and verify the erased sectors

- Embedded Program algorithm automatically writes

and verifies bytes at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

- Reliable operation for the life of the system

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion
of program or erase operations

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector, then
resumes the erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array
data (not available on A290021)

Package options

32-pin P-DIP, PLCC, or TSOP (Forward type)

General Description

The A29002 is a 5.0 volt-only Flash memory organized as
262,144 bytes of 8 bits each. The A29002 offers the

RESET

function, but it is not available on A290021. The 256 Kbytes
of data are further divided into seven sectors for flexible
sector erase capability. The 8 bits of data appear on I/O

I/O

while the addresses are input on A0 to A17. The A29002

is offered in 32-pin PLCC, TSOP, and PDIP packages. This
device is designed to be programmed in-system with the
standard system 5.0 volt VCC supply. Additional 12.0 volt
VPP is not required for in-system write or erase operations.
However, the A29002 can also be programmed in standard
EPROM programmers.
The A29002 has the first toggle bit, I/O

, which indicates

whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O

toggle bit, the

A29002 has a second toggle bit, I/O

, to indicate whether the

addressed sector is being selected for erase. The A29002
also offers the ability to program in the Erase Suspend mode.
The standard A29002 offers access times of 55, 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable (

), write enable (

) and

output enable (

) controls.

The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29002 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper erase margin.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

The host system can detect whether a program or erase
operation is complete by reading the I/O

(

Data

Polling) and

I/O

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29002 is fully erased when shipped
from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors

Pin Configurations

of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data (This feature is not available on the A290021).

DIP

PLCC

RESET

A16

A15

A12

A1
A0

I/O

VSS

I/O

A10

A13

A17

A14

VCC

A11

A29002/A290021

A3
A2

I/O

A10

A29002L/

A290021L

A11

A13

A14

I/O

VSS

I/O

A12

A15

A16

RESET

VCC

A17

NC on A290021

TSOP (Forward type)

A29002V/A290021V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A9
A8

A13
A14
A17

VCC

A16
A15
A12

A7
A6
A5
A4

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

I/O

VSS

I/O

A10

A11

RESET

NC on A290021

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Absolute Maximum Ratings*

Ambient Operating Temperature . . . . . -55

C to + 125

Storage Temperature . . . . . . . . . . . . . . -65

C to + 125

Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V
A9,

& RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V

All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, inputs may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on output and I/O pins is VCC +0.5V. During voltage
transitions, outputs may overshoot to VCC +2.0V for
periods up to 20ns.

2. Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9,

and RESET may overshoot

VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 and

is +12.5V which may

overshoot to 13.5V for periods up to 20ns. (RESET is
N/A on A290021)

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one
second.

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

Operating Ranges

Commercial (C) Devices
Ambient Temperature (T

) . . . . . . . . . . . . . . 0

C to +70

VCC Supply Voltages
VCC for

10% devices . . . . . . . . . . . . . . +4.5V to +5.5V

Operating ranges define those limits between which the
functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to

execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.

Table 1. A29002/A290021 Device Bus Operations

Operation

RESET

(N/A A290021)

A0 A17

I/O

- I/O

Read

OUT

Write

CMOS Standby

VCC

0.5 V

VCC

0.5 V

High-Z

TTL Standby

VCC

0.5 V

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector Unprotect (Note)

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

2. This function is not available on A290021.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive
the

and

pins to V

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at V

all

the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, l

CC1

in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive

and

, and

to V

. An erase operation can erase one

sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O

- I/O

. Standard

read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I

CC2

in the Characteristics table represents the active

current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O

- I/O

. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the

input.
The device enters the CMOS standby mode when the

& RESET pins (

only on A290021) are both held at V

0.5V. (Note that this is a more restricted voltage range

than V

.) The device enters the TTL standby mode when

is held at V

, while RESET (Not available on

A290021) is held at VCC

0.5V. The device requires the

standard access time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I

CC3

in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance
state.

RESET

: Hardware Reset Pin (N/A on A290021)

The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t

, the device

immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Table 2. A29002/A290021 Top Boot Block Sector Address Table

Sector

A17

A16

A15

A14

A13

Sector Size

(Kbytes)

Address Range

SA0

00000h - 0FFFFh

SA1

10000h - 1FFFFh

SA2

20000h - 2FFFFh

SA3

30000h - 37FFFh

SA4

38000h - 39FFFh

SA5

3A000h - 3BFFFh

SA6

3C000h - 3FFFFh

Table 3. A29002/A290021 Bottom Boot Block Sector Address Table

Sector

A17

A16

A15

A14

A13

Sector Size

(Kbytes)

Address Range

SA0

00000h - 03FFFh

SA1

04000h - 05FFFh

SA2

06000h - 07FFFh

SA3

08000h - 0FFFFh

SA4

10000h - 1FFFFh

SA5

20000h - 2FFFFh

SA6

30000h - 3FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O

- I/O

. This mode is primarily

intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes
can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode
requires V

(11.5V to 12.5 V) on address pinA9. Address

pins A6, A1, and AO must be as shown in Autoselect

Codes (High Voltage Method) table. In addition, when
verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O

- I/O

.To access the

autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown
in the Command Definitions table. This method does not
require V

. See "Command Definitions" for details on

using the autoselect mode.

Table 4. A29002/A290021 Autoselect Codes (High Voltage Method)

Description

A17 - A13 A12 - A10 A9 A8 - A7 A6 A5 - A2 A1

Identifier Code on

I/O

- I/O

Manufacturer ID: AMIC

37h

Device ID: A29002/
A290021

Top Boot Block: 8Ch
Bottom Boot Block: 0Dh

01h (protected)

Sector Protection
Verification

Sector

Address

00h (unprotected)

Continuation ID

7Fh

Note: CE

and

when Autoselect Mode

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (V

) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V

power-up transitions, or from system noise. The device is

powered up to read array data to avoid accidentally writing
data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

= V

. To initiate a write cycle,

and

must be a logical zero while

is a logical one.

Power-Up Write Inhibit

= V

and

= V

during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

Temporary Sector Unprotect (N/A on A290021)

This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to V

During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once V

is removed from the RESET pin, all the previously

protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.

START

RESET = V

(Note 1)

Perform Erase or

Program Operations

RESET = V

Temporary Sector

Unprotect

Completed (Note 2)

Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Command Definitions

Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of

whichever happens later. All data is latched on the rising
edge of

, whichever happens first. Refer to the

appropriate timing diagrams in the "AC Characteristics"
section.

Reading Array Data

The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O

goes high, or while in the

autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O

goes high during a program or erase operation, writing

the reset command returns the device to reading array data
(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown in
the Autoselect Codes (High Voltage Method) table, which is
intended for PROM programmers and requires V

address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. The Command
Definitions table shows the address and data requirements
for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O

or I/O

. See "Write

Operation Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot be
programmed from a "0" back to a "1 ". Attempting to do so
may halt the operation and set I/O

to "1", or cause the

Data

Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0" to a
"1".

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O

, I/O

, or I/O

. See

"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50

s begins. During the time-out period, additional

sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50

s, otherwise the last address

and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50

s, the system need not monitor I/O

. Any

command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O

to determine if the sector erase

timer has timed out. (See the " I/O

: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

pulse in the command sequence.

Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O

, I/O

, or I/O

. Refer to "Write

Operation Status" for information on these status bits.

START

Write Program

Command

Sequence

Data Poll

from System

Verify Data ?

Last Address ?

Programming

Completed

Yes

Increment Address

Embedded

Program

algorithm in

progress

Note : See the appropriate Command Definitions table for
program command sequence.

Figure 2. Program Operation

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

START

Write Erase

Command

Sequence

Data Poll

from System

Data = FFh ?

Erasure Completed

Yes

Embedded
Erase
algorithm in
progress

Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O

: Sector Erase Timer" for more information.

Figure 3. Erase Operation

Figure 3 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the
50

s time-out period during the sector erase command

sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
"don't cares" when writing the Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20

s to suspend the erase operation. However, when the

Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O

- I/O

. The system can use I/O

, or I/O

and I/O

together, to

determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O

or I/O

status bits, just

as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Table 5. A29002/A290021 Command Definitions

Bus Cycles (Notes 2 - 4)

First

Second

Third

Fourth

Fifth

Sixth

Command

Sequence

(Note 1)

Cycles

Addr Data Addr Data

Addr Data Addr Data Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

1 XXX

Manufacturer ID

555

2AA

555

X00

Top

Device ID

Bottom

555

2AA

555

X01

Continuation ID

555

2AA

555

X03

Autoselect

(Note 7)

Sector Protect Verify
(Note 8)

555

2AA

555

X02

Program

555

2AA

555

Chip Erase

555

2AA

555

2AA 55

555

Sector Erase

555

2AA

555

2AA 55

Erase Suspend (Note 9)

1 XXX

Erase Resume (Note 10)

1 XXX

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of

pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A13 select a unique sector.

Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A17 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O

goes high

(while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more

information.

9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend

mode.

10. The Erase Resume command is valid only during the Erase Suspend mode.

11. The time between each command cycle has to be less than 50

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Write Operation Status

Several bits, I/O

, I/O

, and I/O

are provided in

the A29002/A290021 to determine the status of a write
operation. Table 6 and the following subsections describe
the functions of these status bits. I/O

, I/O

and I/O

each

offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.

I/O

: Data Polling

The

Data

Polling bit, I/O

, indicates to the host system

whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.

Data

Polling is valid after the rising edge of the final

pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O

the complement of the datum programmed

to I/O

. This I/O

status also applies to programming during

Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
I/O

. The system must provide the program address to

read valid status information on I/O

. If a program address

falls within a protected sector,

Data

Polling on I/O

active for approximately 2

s, then the device returns to

reading array data.
During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O

. When the Embedded Erase

algorithm is complete, or if the device enters the Erase
Suspend mode,

Data

Polling produces a "1" on I/O

.This

is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O

After an erase command sequence is written, if all sectors
selected for erasing are protected,

Data

Polling on I/O

active for approximately 100

s, then the device returns to

reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O

has changed from the

complement to true data, it can read valid data at I/O

- I/O

on the following read cycles. This is because I/O

may

change asynchronously with I/O

- I/O

while Output Enable

(

) is asserted low. The

Data

Polling Timings (During

Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 6 shows the outputs for

Data

Polling on I/O

. Figure 4 shows the

Data

Polling algorithm.

START

Read I/O

-I/O

Address = VA

I/O

= Data ?

FAIL

Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O

should be rechecked even if I/O

= "1" because

I/O

may change simultaneously with I/O

Read I/O

- I/O

Address = VA

I/O

= 1?

I/O

= Data ?

Yes

PASS

Yes

Figure 4. Data Polling Algorithm

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

I/O

: Toggle Bit I

Toggle Bit I on I/O

indicates whether an Embedded

Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final

pulse in the command

sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
I/O

to toggle. (The system may use either

control the read cycles.) When the operation is complete,
I/O

stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O

toggles for

approximately 100

s, then returns to reading array data. If

not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use I/O

and I/O

together to determine

whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O

toggles. When the

device enters the Erase Suspend mode, I/O

stops

toggling. However, the system must also use I/O

determine which sectors are erasing or erase-suspended.
Alternatively, the system can use I/O

(see the subsection

on " I/O

Data

Polling").

If a program address falls within a protected sector, I/O

toggles for approximately 2

s after the program command

sequence is written, then returns to reading array data.
I/O

also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O

. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O

vs.

I/O

figure shows the differences between I/O

and I/O

graphical form. See also the subsection on " I/O

: Toggle

Bit II".

I/O

: Toggle Bit II

The "Toggle Bit II" on I/O

, when used with I/O

, indicates

whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final

pulse in the command

sequence.
I/O

toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The
system may use either

to control the read

cycles.) But I/O

cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O

, by

comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status

bits are required for sector and mode information. Refer to
Table 6 to compare outputs for I/O

and I/O

Figure 5 shows the toggle bit algorithm in flowchart form,
and the section " I/O

: Toggle Bit II" explains the algorithm.

See also the " I/O

: Toggle Bit I" subsection. Refer to the

Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O

vs. I/O

figure shows the differences between I/O

and I/O

in graphical form.

Reading Toggle Bits I/O

, I/O

Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O

- I/O

at least twice in a row to determine whether

a toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on I/O

- I/O

on the

following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O

is high (see the

section on I/O

). If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O

went high. If the

toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O

has not

gone high. The system may continue to monitor the toggle
bit and I/O

through successive read cycles, determining

the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 5).

I/O

: Exceeded Timing Limits

I/O

indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under
these conditions I/O

produces a "1." This is a failure

condition that indicates the program or erase cycle was not
successfully completed.
The I/O

failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation,
and when the operation has exceeded the timing limits,
I/O

produces a "1."

Under both these conditions, the system must issue the
reset command to return the device to reading array data.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

I/O

: Sector Erase Timer

After writing a sector erase command sequence, the
system may read I/O

to determine whether or not an

erase operation has begun. (The sector erase timer does
not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, I/O

switches from "0" to

"1." The system may ignore I/O

if the system can

guarantee that the time between additional sector erase
commands will always be less than 50

s. See also the

"Sector Erase Command Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O

(

Data

Polling) or

I/O

(Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O

. If I/O

is "1", the

internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until
the erase operation is complete. If I/O

is "0", the device

will accept additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of I/O

prior to and following each

subsequent sector erase command. If I/O

is high on the

second status check, the last command might not have
been accepted. Table 6 shows the outputs for I/O

START

Read I/O

-I/O

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O

changes to "1". See text.

Read I/O

- I/O

Twice

I/O

= 1?

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Complete

Read I/O

-I/O

(Notes 1,2)

Figure 5. Toggle Bit Algorithm

(Note 1)

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

DC Characteristics

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

Input Load Current

= VSS to VCC. VCC = VCC Max

1.0

LIT

A9,

RESET

Input Load Current

VCC = VCC Max,
A9,

RESET

=12.5V

100

Output Leakage Current

OUT

= VSS to VCC. VCC = VCC Max

1.0

CC1

VCC Active Read Current
(Notes 1, 2)

= V

CC2

VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)

= V

CC3

VCC Standby Current (Note 2)

= V

RESET

= VCC

0.5V

0.4

1.0

Input Low Level

-0.5

0.8

Input High Level

2.0

VCC+0.5 V

Voltage for Autoselect and
Temporary Unprotect Sector

VCC = 5.25 V

10.5

12.5

Output Low Voltage

= 12mA, VCC = VCC Min

0.45

Output High Voltage

= -2.5 mA, VCC = VCC Min

2.4

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

Input Load Current

= VSS to VCC, VCC = VCC Max

1.0

LIT

A9,

RESET

Input Load Current

VCC = VCC Max,
A9,

RESET

= 12.5V

100

Output Leakage Current

OUT

= VSS to VCC, VCC = VCC Max

1.0

CC1

VCC Active Read Current

(Notes 1,2)

= V

CC2

VCC Active Program/Erase Current

(Notes 2,3,4)

= V

CC3

VCC Standby Current (Notes 2, 5)

RESET

= VCC

0.5 V

Input Low Level

-0.5

0.8

Input High Level

0.7 x VCC

VCC+0.3 V

Voltage for Autoselect and
Temporary Sector Unprotect

VCC = 5.25 V

10.5

12.5

Output Low Voltage

= 12.0 mA, VCC = VCC Min

0.45

OH1

= -2.5 mA, VCC = VCC Min

0.85 x VCC

OH2

Output High Voltage

= -100

A. VCC = VCC Min

VCC-0.4

Notes for DC characteristics (both tables):
1. The I

current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with

at V

2. Maximum I

specifications are tested with VCC = VCC max.

3. I

active while Embedded Algorithm (program or erase) is in progress.

4. Not 100% tested.
5. For CMOS mode only, I

CC3

= 20

A max at extended temperatures (> +85

C).

RESET

is not available on A290021.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

AC Characteristics

Read Only Operations

Parameter Symbols

Speed

JEDEC

Std

Description

Test Setup

-55

-70

-90 -120 -150

Unit

AVAV

Read Cycle Time (Note 2)

Min.

120

150

AVQV

ACC

Address to Output Delay

= V

Max. 55

120

150

ELQV

Chip Enable to Output Delay

= V

Max. 55

120

150

GLQV

Output Enable to Output Delay

Max. 30

Read

Min.

OEH

Output Enable Hold
Time (Note 2)

Toggle and

Data

Polling

Min.

EHQZ

Chip Enable to Output High Z
(Notes 1,2)

Max.

GHQZ

Output Enable to Output High Z
(Notes 1,2)

AXQX

Output Hold Time from Addresses,

, Whichever Occurs First

Min.

Notes:
1. Output driver disable time.
2. Not 100% tested.

Timing Waveforms for Read Only Operation (RESET

on A29002)

Addresses

Addresses Stable

Output Valid

High-Z

Output

OEH

High-Z

ACC

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

CE, OE

RESET

Ready

Reset Timings NOT during Embedded Algorithms

RESET

Reset Timings during Embedded Algorithms

Program or Erase Command Sequence

RESET

12V

0 or 5V

VIDR

0 or 5V

RSP

Hardware Reset (RESET

)

(N/A on A290021)

Parameter

JEDEC

Std

Description

Test Setup

All Speed Options

Unit

READY

RESET

Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

Max

READY

RESET

Pin Low (Not During Embedded

Algorithms) to Read or Write (See Note)

Max

500

RESET

Pulse Width

Min

500

RESET

High Time Before Read (See Note)

Min

Note: Not 100% tested.

RESET Timings

Temporary Sector Unprotect (N/A on A290021)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

VIDR

Rise and Fall Time (See Note)

Min

500

RSP

RESET

Setup Time for Temporary Sector

Unprotect

Min

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

AC Characteristics

Erase and Program Operations

Parameter Symbols

Speed

JEDEC

Std

Description

-55

-70

-90 -120 -150

Unit

AVAV

Write Cycle Time (Note 1)

Min.

120

150

AVWL

Address Setup Time

Min.

WLAX

Address Hold Time

Min.

DVWH

Data Setup Time

Min.

WHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

GHWL

Read Recover Time Before Write
(

high to

low)

Min.

ELWL

Setup Time

Min.

WHEH

Hold Time

Min.

WLWH

Write Pulse Width

Min.

WHWL

WPH

Write Pulse Width High

Max.

WHWH1

Byte Programming Operation
(Note 2)

Typ.

WHWH2

Sector Erase Operation
(Note 2)

Typ.

sec

VCS

VCC Set Up Time (Note 1)

Min.

Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Timing Waveforms for I/O

vs. I/O

AC Characteristics

Erase and Program Operations

Alternate

Controlled Writes

Parameter Symbols

Speed

JEDEC

Std

Description

-55

-70

-90

-120

-150

Unit

AVAV

Write Cycle Time (Note 1)

Min.

120

150

AVEL

Address Setup Time

Min.

ELAX

Address Hold Time

Min.

DVEH

Data Setup Time

Min.

EHDX

Data Hold Time

Min.

GHEL

Read Recover Time Before Write

Min.

WLEL

Setup Time

Min.

EHWH

Hold Time

Min.

ELEH

Write Pulse Width

Min.

EHEL

CPH

Write Pulse Width High

Min.

WHWH1

Byte Programming Operation
(Note 2)

Typ.

WHWH2

Sector Erase Operation
(Note 2)

Typ.

sec

Notes:
3. Not 100% tested.
4. See the "Erase and Programming Performance" section for more information.

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

I/O

Erase

Erase Suspend

Read

Erase Suspend

Read

Erase

Complete

I/O

and I/O

toggle with OE and CE

Note : Both I/O

and I/O

toggle with OE or CE. See the text on I/O

and I/O

in the section "Write Operation Statue" for

more information.

~ ~

Erase

Suspend

Program

~ ~

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Timing Waveforms for Alternate CE Controlled Write Operation (

RESET

on A29002)

Erase and Programming Performance

Parameter

Typ. (Note 1)

Max. (Note 2)

Unit

Comments

Sector Erase Time

sec

Chip Erase Time

sec

Excludes 00h programming
prior to erasure (Note 4)

Byte Programming Time

300

Chip Programming Time (Note 3)

3.6

10.8

sec

Excludes system-level
overhead (Note 5)

Notes:
1. Typical program and erase times assume the following conditions: 25

C, 5.0V VCC, 100,000 cycles. Additionally,

programming typically assumes checkerboard pattern.

2. Under worst case conditions of 90

C, VCC = 4.5V (4.75V for -55), 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only
then does the device set I/O

= 1. See the section on I/O

for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See

Table 4 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

Addresses

Data

555 for program

2AA for erase

OUT

~ ~

I/O

~ ~

Data Polling

Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

= Complement of Data Input, D

OUT

= Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

PD for program
30 for sector erase
10 for chip erase

~ ~

BUSY

WHWH1 or 2

GHEL

CPH

PA for program
SA for sector erase
555 for chip erase

A0 for program
55 for erase

A29002/A290021 Series

(December, 2002, Version 1.1)

AMIC Technology, Corp.

Latch-up Characteristics

Description

Min.

Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V

VCC Current

-100 mA

+100 mA

Input voltage with respect to VSS on all pins except I/O pins
(including A9,

and

RESET

)

-1.0V

12.5V

Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.

RESET

N/A on A290021

TSOP Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

7.5

OUT

Output Capacitance

OUT

8.5

IN2

Control Pin Capacitance

7.5

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25

C, f = 1.0MHz

PLCC and P-DIP Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input Capacitance

OUT

Output Capacitance

OUT

IN2

Control Pin Capacitance

Notes:
3. Sampled, not 100% tested.
4. Test conditions T

= 25

C, f = 1.0MHz

Data Retention

Parameter

Test Conditions

Min

Unit

150

Years

Minimum Pattern Data Retention Time

125

Years

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A29002L-150