A29DL32x Series

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,

Preliminary

Simultaneous Operation Flash Memory

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Simultaneous Read/Write operations

- Data can be continuously read from one bank while

executing erase/program functions in other bank

- Zero latency between read and write operations

Multiple bank architectures

- Three devices available with different bank sizes (refer to

Table 2)

Package options

48-ball TFBGA

48-pin TSOP

Top or bottom boot block
Manufactured on 0.18 祄 process technology

- Compatible with AMD AM29DL32xD device

Compatible with JEDEC standards

Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

High performance

Access time as fast as 70ns

Program time: 7祍/word typical utilizing Accelerate

function

Ultra low power consumption (typical values)

2mA active read current at 1MHz

10mA active read current at 5MHz

200nA in standby or automatic sleep mode

Minimum 1 million write cycles guaranteed per sector

20 Year data retention at 125癈

Reliable operation for the life of the system

SOFTWARE FEATURES

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

Suspends erase operations to allow programming in

same bank

Data

Polling and Toggle Bits

Provides a software method of detecting the status of
program or erase cycles

Unlock Bypass Program command

Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

Any combination of sectors can be erased

Ready/

Busy

output (RY/

)

- Hardware method for detecting program or erase cycle

completion

Hardware reset pin (RESET )

- Hardware method of resetting the internal state machine

to reading array data

/ACC input pin

- Write protect (

) function allows protection of two

outermost boot sectors, regardless of sector protect
status

- Acceleration (ACC) function accelerates program timing

Sector protection

- Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program
or erase operation within that sector

- Temporary Sector Unprotect allows changing data in

protected sectors in-system

Software temporary sector/sector block unprotect command

Software sector protect/unprotect command

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

GENERAL DESCRIPTION

The A29DL32x family consists of 32 megabit, 3.0 volt-only
flash memory devices, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word mode data
appears on I/O

璉/O

; byte mode data appears on I/O

璉/O

The device is designed to be programmed in-system with the
standard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The device is available with an access time of 70, 80, 90, or
120 ns. The devices are offered in 48-pin TSOP and 48-ball
Fine-pitch TFBGA. Standard control pins--chip enable (

write enable (

), and output enable (

)--control

normal read and write operations, and avoid bus contention
issues.

The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.

Simultaneous Read/Write Operations with Zero
Latency

The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A29DL32x devices use multiple bank architectures to
provide flexibility for different applications. Three devices are
available with these bank sizes:

Device

Bank 1

Bank 2

DL322

4 Mb

28 Mb

DL323

8 Mb

24 Mb

DL324 16 Mb

16 Mb

A29DL32x Features

The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/

pin, I/O

(

Data

Polling) and I/O

/I/O

(toggle bits).

After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the

command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.

Table 1. A29DL32x Device Bus Operations

I/O

- I/O

Operation

RESET

/ACC

A0 � A20

(Note 1)

I/O

- I/O

BYTE

Read L

L/H

OUT

I/O

~I/O

=High-Z

Write L

(Note

I/O

~I/O

=High-Z

I/O

=A-1

Standby

VCC

�

0.3 V

X X

VCC

�

0.3 V

H X

High-Z

Output Disable

L/H

High-Z

Reset X

L/H

High-Z

Sector Protect
(See Note 2)

L H L V

L/H

SA, A6=L,

A1=H, A0=L

Sector Unprotect
(See Note 2)

L H L V

(Note

SA, A6=H,

A1=H, A0=L

Temporary Sector
Unprotect

X X X V

(Note

High-Z

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 8.5 -12.5V, V

= 9.0 � 0.5 V, X = Don't Care, SA = Sector Address, A

Address In, D

= Data In, D

OUT

= Data Out

Notes:
1. Addresses are A20:A0 in word mode (

BYTE

), A20: A-1 in byte mode (

BYTE

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

"Sector/Sector Block Protection and Unprotection" section.

3. If

/ACC = V

, the two outermost boot sectors remain protected. If

/ACC = V

, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block
Protection and Unprotection". If

/ACC = V

all sectors will be unprotected.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Word/Byte Configuration

The

BYTE

pin determines whether the I/O pins I/O

-I/O

operate in the byte or word configuration. If the

BYTE

pin is

set at logic "1", the device is in word configuration, I/O

-I/O

are active and controlled by

and

If the

BYTE

pin is set at logic "0", the device is in byte

configuration, and only I/O

-I/O

are active and controlled by

and

. I/O

-I/O

are tri-stated, and I/O

pin is used

as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive
the

and

pins to V

is the power control and

selects the device.

is the output control and gates array

data to the output pins.

should remain at V

. The

BYTE

pin determines whether the device outputs array data

in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, l

CC1

in the DC Characteristics table represents the

active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive

and

to V

, and

to V

For program operations, the

BYTE

pin determines whether

the device accepts program data in bytes or words, Refer to
"Word/Byte Configuration" for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The "Word / Byte Program Command
Sequence" section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A "bank address" is the address bits
required to uniquely select a bank. Similarly, a "sector
address" is the address bits required to uniquely select a
sector.
I

CC2

in the DC Characteristics table represents the active

current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Accelerated Program Operation
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the

/ACC pin. This function is primarily intended to allow

faster manufacturing throughput at the factory.
If the system asserts V

on this pin, the device automatically

enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing V

from the

/ACC pin returns the

device to normal operation. Note that the

/ACC pin must

not be at V

for operations other than accelerated program-

ming, or device damage may result. In addition, the

/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O

-I/O

. Standard read

cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.

Simultaneous Read/Write Operations with Zero
Latency

This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. I

CC6

and I

CC7

in the DC Characteristics

table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the

input.
The device enters the CMOS standby mode when the

RESET pins are both held at VCC

�

0.3V. (Note that this is a

more restricted voltage range than V

.) If

and RESET

are held at V

, but not within VCC

�

0.3V, the device will be

in the standby mode, but the standby current will be greater.
The device requires the standard access time (t

) for read

access when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I

CC3

in the DC Characteristics tables represent the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t

ACC

+30ns. The automatic

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

sleep mode is independent of the

and

control

signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. I

CC4

in the

DC Characteristics table represents the automatic sleep
mode current specification.

RESET

: Hardware Reset Pin

The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the

RESET pin low for at least a period of t

, the device

immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS

�

0.3V, the device draws

CMOS standby current (I

CC4

). If RESET is held at V

but not

within VSS

�

0.3V, the standby current will be greater.

The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/

pin remains a "0" (busy) until the internal reset

operation is complete, which requires a time t

READY

(during

Embedded Algorithms). The system can thus monitor
RY/

to determine whether the reset operation is

complete. If RESET is asserted when a program or erase
operation is not executing (RY/

pin is "1"), the reset

operation is completed within a time of t

READY

(not during

Embedded Algorithms). The system can read data t

after

the RESET pin return to V

Refer to the AC Characteristics tables for RESET
parameters and diagram.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance
state.

Table 2. A29DL32x Device Bank Divisions

Bank 1

Bank 2

Device

Part Number

Megabits

Sector Sizes

Megabits

Sector Sizes

A29DL322

4 Mbit

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

28 Mbit

Fifty-six

64 Kbyte/32 Kword

A29DL323

8 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

24 Mbit

Forty-eight

64 Kbyte/32 Kword

A29DL324

16 Mbit

Eight 8 Kbyte/4 Kword,

Thirty one 64 Kbyte/32 Kword

16 Mbit

Thirty-two

64 Kbyte/32 Kword

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Table 3 Sector Addresses for Top Boot Sector Devices

A29DL

24T

A29DL

23T

A29DL

22T

Sector

Sector Address

A20瑼12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000XXX

64/32

000000h-00FFFFh

000000h�007FFFh

SA1

000001XXX

64/32

010000h-01FFFFh

008000h�00FFFFh

SA2

000010XXX

64/32 020000h-02FFFFh

010000h�017FFFh

SA3

000011XXX

64/32

030000h-03FFFFh

018000h�1FFFFFh

SA4

000100XXX

64/32

040000h-04FFFFh

020000h�027FFFh

SA5

000101XXX

64/32

050000h-05FFFFh

028000h�02FFFFh

SA6

000110XXX

64/32

060000h-06FFFFh

030000h�037FFFh

SA7

000111XXX

64/32

070000h-07FFFFh

038000h�03FFFFh

SA8

001000XXX

64/32

080000h-08FFFFh

040000h�047FFFh

SA9

001001XXX

64/32

090000h-09FFFFh

048000h�04FFFFh

SA10

001010XXX

64/32

0A0000h-0AFFFFh

050000h�057FFFh

SA11

001011XXX

64/32

0B0000h-0BFFFFh

058000h�05FFFFh

SA12

001100XXX

64/32

0C0000h-0CFFFFh

060000h�067FFFh

SA13

001101XXX

64/32

0D0000h-0DFFFFh

068000h�06FFFFh

SA14

001110XXX

64/32

0E0000h-0EFFFFh

070000h�077FFFh

SA15

001111XXX

64/32

0F0000h-0FFFFFh

078000h�07FFFFh

SA16

010000XXX

64/32

100000h-10FFFFh 080000h�087FFFh

SA17

010001XXX

64/32

110000h-11FFFFh

088000h�08FFFFh

SA18

010010XXX

64/32

120000h-12FFFFh 090000h�097FFFh

SA19

010011XXX

64/32

130000h-13FFFFh

098000h�09FFFFh

SA20

010100XXX

64/32

140000h-14FFFFh

0A0000h�0A7FFFh

SA21

010101XXX

64/32

150000h-15FFFFh

0A8000h�0AFFFFh

SA22

010110XXX

64/32

160000h-16FFFFh

0B0000h�0B7FFFh

SA23

010111XXX

64/32

170000h-17FFFFh

0B8000h�0BFFFFh

SA24

011000XXX

64/32

180000h-18FFFFh

0C0000h�0C7FFFh

SA25

011001XXX

64/32

190000h-19FFFFh

0C8000h�0CFFFFh

SA26

011010XXX

64/32

1A0000h-1AFFFFh

0D0000h�0D7FFFh

SA27

011011XXX

64/32

1B0000h-1BFFFFh

0D8000h�0DFFFFh

SA28

011100XXX

64/32

1C0000h-1CFFFFh

0E0000h�0E7FFFh

SA29

011101XXX

64/32

1D0000h-1DFFFFh

0E8000h�0EFFFFh

SA30

011110XXX

64/32

1E0000h-1EFFFFh

0F0000h�0F7FFFh

Bank 2

SA31

011111XXX

64/32

1F0000h-1FFFFFh

0F8000h�0FFFFFh

SA32

100000XXX

64/32

200000h-20FFFFh

100000h�107FFFh

SA33

100001XXX

64/32

210000h-21FFFFh

108000h�10FFFFh

SA34

100010XXX

64/32

220000h-22FFFFh

110000h�117FFFh

SA35

100011XXX

64/32

230000h-23FFFFh

118000h�11FFFFh

SA36

100100XXX

64/32

240000h-24FFFFh

120000h�127FFFh

SA37

100101XXX

64/32

250000h-25FFFFh

128000h�12FFFFh

SA38

100110XXX

64/32 260000h-26FFFFh

130000h�137FFFh

SA39 100111XXX

64/32 270000h-27FFFFh

138000h�13FFFFh

SA40 101000XXX

64/32 280000h-28FFFFh 140000h�147FFFh

SA41 101001XXX

64/32 290000h-29FFFFh

148000h�14FFFFh

SA42 101010XXX

64/32 2A0000h-2AFFFFh 150000h�157FFFh

SA43 101011XXX

64/32 2B0000h-2BFFFFh 158000h�15FFFFh

SA44 101100XXX

64/32 2C0000h-2CFFFFh 160000h�167FFFh

SA45 101101XXX

64/32 2D0000h-2DFFFFh

168000h�16FFFFh

SA46 101110XXX

64/32 2E0000h-2EFFFFh 170000h�177FFFh

Bank 1

Bank 2

SA47 101111XXX

64/32 2F0000h-2FFFFFh

178000h�17FFFFh

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Table 3 Sector Addresses for Top Boot Sector Devices

A29DL

24T

A29DL

23T

A29DL

22T

Sector

Sector Address

A20瑼12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA48 110000XXX

64/32

300000h-30FFFFh

180000h�187FFFh

SA49 110001XXX

64/32

310000h-31FFFFh 188000h�18FFFFh

SA50 110010XXX

64/32

320000h-32FFFFh

190000h�197FFFh

SA51 110011XXX

64/32

330000h-33FFFFh 198000h�19FFFFh

SA52 110100XXX

64/32

340000h-34FFFFh 1A0000h�1A7FFFh

SA53

110101XXX

64/32

350000h-35FFFFh 1A8000h�1AFFFFh

SA54 110110XXX

64/32

360000h-36FFFFh 1B0000h�1B7FFFh

Bank 2

SA55 110111XXX

64/32

370000h-37FFFFh 1B8000h�1BFFFFh

SA56 111000XXX

64/32

380000h-38FFFFh 1C0000h�1C7FFFh

SA57 111001XXX

64/32

390000h-39FFFFh 1C8000h�1CFFFFh

SA58 111010XXX

64/32

3A0000h-3AFFFFh 1D0000h�1D7FFFh

SA59 111011XXX

64/32

3B0000h-3BFFFFh 1D8000h�1DFFFFh

SA60 111100XXX

64/32

3C0000h-3CFFFFh 1E0000h�1E7FFFh

SA61 111101XXX

64/32

3D0000h-3DFFFFh 1E8000h�1EFFFFh

SA62 111110XXX

64/32

3E0000h-3EFFFFh 1F0000h�1F7FFFh

SA63 111111000

8/4

3F0000h-3FFFFFh 1F8000h�1F8FFFh

SA64 111111001

8/4 3F2000h-3F3FFFh 1F9000h�1F9FFFh

SA65 111111010

8/4 3F4000h-3F5FFFh 1FA000h�1FAFFFh

SA66 111111011

8/4 3F6000h-3F7FFFh 1FB000h�1FBFFFh

SA67

111111100

8/4

3F8000h-3F9FFFh 1FC000h�1FCFFFh

SA68 111111101

8/4 3FA000h-3FBFFFh 1FD000h�1FDFFFh

SA69 111111110

8/4 3FC000h-3FDFFFh 1FE000h�1FEFFFh

Bank 1

SA70 111111111

8/4 3FE000h-3FFFFFh 1FF000h�1FFFFFh

The address range is A20: A-1in byte mode (

BYTE

) or A20:A0 in word mode (

BYTE

). The bank address bits are A20-

A18 for A29DL322T, A20 and A19 for A29DL323T, and A20 for A29DL324T.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Table 4. Sector Addresses for Bottom Boot Sector Devices

A29DL

24U

A29DL

23U

A29DL

22U

Sector

Sector Address

A20瑼12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000000

8/4

000000h-001FFFh

000000h-000FFFh

SA1

000000001

8/4

002000h-003FFFh

001000h-001FFFh

SA2

000000010

8/4

004000h-005FFFh

002000h-002FFFh

SA3

000000011

8/4

006000h-007FFFh

003000h-003FFFh

SA4

000000100

8/4

008000h-009FFFh

004000h-004FFFh

SA5

000000101

8/4

00A000h-00BFFFh

005000h-005FFFh

SA6

000000110

8/4

00C000h-00DFFFh

006000h-006FFFh

SA7

000000111

8/4

00E000h-00FFFFh

007000h-007FFFh

SA8

000001XXX

64/32

010000h-01FFFFh

008000h-00FFFFh

SA9

000010XXX

64/32

020000h-02FFFFh

010000h-017FFFh

SA10

000011XXX

64/32

030000h-03FFFFh

018000h-01FFFFh

SA11

000100XXX

64/32

040000h-04FFFFh

020000h-027FFFh

SA12

000101XXX

64/32

050000h-05FFFFh

028000h-02FFFFh

SA13

000110XXX

64/32

060000h-06FFFFh

030000h-037FFFh

Bank 1

SA14

000111XXX

64/32

070000h-07FFFFh

038000h-03FFFFh

SA15

001000XXX

64/32

080000h-08FFFFh

040000h-047FFFh

SA16

001001XXX

64/32

090000h-09FFFFh

048000h-04FFFFh

SA17

001010XXX

64/32

0A0000h-0AFFFFh

050000h-057FFFh

SA18

001011XXX

64/32

0B0000h-0BFFFFh

058000h-05FFFFh

SA19

001100XXX

64/32

0C0000h-0CFFFFh

060000h-067FFFh

SA20

001101XXX

64/32

0D0000h-0DFFFFh

068000h-06FFFFh

SA21

001110XXX

64/32

0E0000h-0EFFFFh

070000h-077FFFh

Bank 1

SA22

001111XXX

64/32

0F0000h-0FFFFFh

078000h-07FFFFh

SA23

010000XXX

64/32

100000h-10FFFFh

080000h-087FFFh

SA24

010001XXX

64/32

110000h-11FFFFh

088000h-08FFFFh

SA25

010010XXX

64/32

120000h-12FFFFh

090000h-097FFFh

SA26

010011XXX

64/32

130000h-13FFFFh

098000h-09FFFFh

SA27

010100XXX

64/32

140000h-14FFFFh

0A0000h-0A7FFFh

SA28

010101XXX

64/32

150000h-15FFFFh

0A8000h-0AFFFFh

SA29

010110XXX

64/32

160000h-16FFFFh

0B0000h-0B7FFFh

SA30

010111XXX

64/32

170000h-17FFFFh

0B8000h-0BFFFFh

SA31

011000XXX

64/32

180000h-18FFFFh

0C0000h-0C7FFFh

SA32

011001XXX

64/32

190000h-19FFFFh

0C8000h-0CFFFFh

SA33

011010XXX

64/32 1A0000h-1AFFFFh

0D0000h-0D7FFFh

SA34

011011XXX

64/32 1B0000h-1BFFFFh

0D8000h-0DFFFFh

SA35

011100XXX

64/32

1C0000h-1CFFFFh

0E0000h-0E7FFFh

SA36

011101XXX

64/32

1D0000h-1DFFFFh

0E8000h-0EFFFFh

SA37

011110XXX

64/32

1E0000h-1EFFFFh

0F0000h-0F7FFFh

SA38

011111XXX

64/32

1F0000h-1FFFFFh

0F8000h-0FFFFFh

Bank 2

SA39

100000XXX

64/32

200000h-20FFFFh

100000h-107FFFh

SA40

100001XXX

64/32

210000h-21FFFFh

108000h-10FFFFh

SA41

100010XXX

64/32

220000h-22FFFFh

110000h-117FFFh

SA42

100011XXX

64/32

230000h-23FFFFh

118000h-11FFFFh

SA43

100100XXX

64/32

240000h-24FFFFh

120000h-127FFFh

SA44

100101XXX

64/32

250000h-25FFFFh

128000h-12FFFFh

SA45

100110XXX

64/32

260000h-26FFFFh

130000h-137FFFh

SA46

100111XXX

64/32

270000h-27FFFFh

138000h-13FFFFh

Bank 2

SA47 101000XXX

64/32

280000h-28FFFFh

140000h-147FFFh

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

A29DL

24U

A29DL

23U

A29DL

22U

Sector

Sector Address

A20瑼12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA48

101001XXX

64/32

290000h-29FFFFh

148000h-14FFFFh

SA49 101010XXX

64/32 2A0000h-2AFFFFh

150000h-157FFFh

SA50 101011XXX

64/32 2B0000h-2BFFFFh

158000h-15FFFFh

SA51

101100XXX

64/32

2C0000h-2CFFFFh

160000h-167FFFh

SA52

101101XXX

64/32

2D0000h-2DFFFFh

168000h-16FFFFh

SA53

101110XXX

64/32 2E0000h-2EFFFFh

170000h-177FFFh

SA54

101111XXX

64/32

2F0000h-2FFFFFh

178000h-17FFFFh

SA55

110000XXX

64/32

300000h-30FFFFh

180000h-187FFFh

SA56

110001XXX

64/32

310000h-31FFFFh

188000h-18FFFFh

SA57

110010XXX

64/32

320000h-32FFFFh

190000h-197FFFh

SA58

110011XXX

64/32

330000h-33FFFFh

198000h-19FFFFh

SA59 110100XXX

64/32

340000h-34FFFFh

1A0000h-1A7FFFh

SA60 110101XXX

64/32

350000h-35FFFFh

1A8000h-1AFFFFh

SA61 110110XXX

64/32

360000h-36FFFFh

1B0000h-1B7FFFh

SA62

110111XXX

64/32

370000h-37FFFFh

1B8000h-1BFFFFh

SA63

111000XXX

64/32

380000h-38FFFFh

1C0000h-1C7FFFh

SA64

111001XXX

64/32

390000h-39FFFFh

1C8000h-1CFFFFh

SA65

111010XXX

64/32 3A0000h-3AFFFFh

1D0000h-1D7FFFh

SA66 111011XXX

64/32

3B0000h-3BFFFFh

1D8000h-1DFFFFh

SA67 111100XXX

64/32

3C0000h-3CFFFFh

1E0000h-1E7FFFh

SA68

111101XXX

64/32

3D0000h-3DFFFFh

1E8000h-1EFFFFh

SA69

111110XXX

64/32

3E0000h-3EFFFFh

1F0000h-1F7FFFh

Bank 2

SA70

111111XXX

64/32

3F0000h-3FFFFFh

1F8000h-1FFFFFh

Note:
The address range is A20: A-1in byte mode (

BYTE

) or A20:A0 in word mode (

BYTE

). The bank address bits are A20-

A18 for A29DL322U, A20 and A19 for A29DL323U, and A20 for A29DL324U.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Autoselect Mode

The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O

- I/O

. This mode is primarily

intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires V

(8.5V to 12.5 V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Table 5. In
addition, when verifying sector protection, the sector address

must appear on the appropriate highest order address bits.
(see Table 3-4). Table 5 shows the remaining address bits
that are don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O

- I/O

To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 12. This method does not require
V

. Refer to the Autoselect Command Sequence section for

more information.

Table 5. A29DL32x Autoselect Codes (High Voltage Method)

I/O

to I/O

Description

A20

A12

A11

A10

BYTE

= V

BYTE

= V

I/O

Manufacturer ID:
AMIC

37h

Device ID: A29DL322

22h

55h (T), 56h (U)

Device ID: A29DL323

22h

50h (T), 53h (U)

Device ID: A29DL324

22h

5Ch (T), 5Fh (U)

Continuation ID

H X X

7Fh

Read Sector Status

01h (protected),

00h (unprotected)

L=Logic Low= V

, H=Logic High=V

, SA=Sector Address, X=Don't Care, BA=Bank Address

Note: The autoselect codes may also be accessed in-system via command sequences.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Sector/Sector Block Protection and Unprotection

Table 6. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection

Sector /

Sector Block

A20瑼12

Sector / Sector Block Size

SA0

000000XXX

64 Kbytes

SA1-SA3

000001XXX,
000010XXX,

000011XXX

192 (3x64) Kbytes

SA4-SA7

0001XXXXX

256 (4x64) Kbytes

SA8-SA11

0010XXXXX

256 (4x64) Kbytes

SA12-SA15

0011XXXXX

256 (4x64) Kbytes

SA16-SA19

0100XXXXX

256 (4x64) Kbytes

SA20-SA23

0101XXXXX

256 (4x64) Kbytes

SA24-SA27

0110XXXXX

256 (4x64) Kbytes

SA28-SA31

0111XXXXX

256 (4x64) Kbytes

SA32-SA35

1000XXXXX

256 (4x64) Kbytes

SA36-SA39

1001XXXXX

256 (4x64) Kbytes

SA40-SA43

1010XXXXX

256 (4x64) Kbytes

SA44-SA47

1011XXXXX

256 (4x64) Kbytes

SA48-SA51

1100XXXXX

256 (4x64) Kbytes

SA52-SA55

1101XXXXX

256 (4x64) Kbytes

SA56-SA59

1110XXXXX

256 (4x64) Kbytes

SA60-SA62

111100XXX,
111101XXX,

111110XXX

192 (3x64) Kbytes

SA63 111111000

Kbytes

SA64 111111001

Kbytes

SA65 111111010

Kbytes

SA66 111111011

Kbytes

SA67 111111100

Kbytes

SA68 111111101

Kbytes

SA69 111111110

Kbytes

SA70 111111111

Kbytes

Table 7. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection

Sector /

Sector Block

A20瑼12

Sector / Sector Block Size

SA70 111111XXXX

Kbytes

SA69- SA67

111110XXX,
111101XXX,

111100XXX

192 (3x64) Kbytes

SA66- SA63

1110XXXXX

256 (4x64) Kbytes

SA62- SA59

1101XXXXX

256 (4x64) Kbytes

SA58- SA55

1100XXXXX

256 (4x64) Kbytes

SA54- SA51

1011XXXXX

256 (4x64) Kbytes

SA50- SA47

1010XXXXX

256 (4x64) Kbytes

SA46-SA43

1001XXXXX

256 (4x64) Kbytes

SA42-SA39

1000XXXXX

256 (4x64) Kbytes

SA38-SA35

0111XXXXX

256 (4x64) Kbytes

SA34-SA31

0110XXXXX

256 (4x64) Kbytes

SA30-SA27

0101XXXXX

256 (4x64) Kbytes

SA26-SA23

0100XXXXX

256 (4x64) Kbytes

SA22-SA19

0011XXXXX

256 (4x64) Kbytes

SA18-SA15

0010XXXXX

256 (4x64) Kbytes

SA14-SA11

0001XXXXX

256 (4x64) Kbytes

SA10-SA8

000001XXX,
000010XXX,

000011XXX

192 (3x64) Kbytes

SA7 000000111

Kbytes

SA6 000000110

Kbytes

SA5 000000101

Kbytes

SA4 000000100

Kbytes

SA3 000000011

Kbytes

SA2 000000010

Kbytes

SA1 000000001

Kbytes

SA0 000000000

Kbytes

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors. Sector
protection and unprotection can be implemented via two
methods.
The primary method requires V

on the RESET pin only,

and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and
Figure 23 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually
re-protected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available. See
"Temporary Sector/Sector Block Unprotect".
The alternate method for protection and unprotection is by
software sector /sector block protect unprotect command.
See Figure 2 for Command Flow.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See the Autoselect Mode section for details.

Write Protect (

)

The Write Protect function provides a hardware method of
protecting certain boot sectors without using V

. This

function is one of two provided by the

/ACC pin.

If the system asserts V

on the

/ACC pin, the device

disables program and erase functions in the two "outermost"
8 Kbyte boot sectors independently of whether those sectors
were protected or unprotected using the method described in

"Sector/Sector Block Protection and Unprotection". The two
outermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured
device, or the two sectors containing the highest addresses
in a top-boot-configured device.
If the system asserts V

on the

/ACC pin, the device

reverts to whether the two outermost 8 Kbyte boot sectors
were last set to be protected or unprotected. That is, sector
protection or unprotection for these two sectors depends on
whether they were last protected or unprotected using the
method described in "Sector/Sector Block Protection and
Unprotection".
Note that the

/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may result.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term "sector" applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to V

(8.5V-12.5V). During this mode, formerly protected sectors
can be programmed or erased by selecting the sector
addresses. Once V

is removed from the RESET pin, all the

previously protected sectors are protected again. Figure 1
shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

START

PLSCNT=1

RESET=V

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address
with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Data=01h?**

Protect another

sector?

Remove V

from RESET

Write reset

command

Sector Protect

complete

Sector Protect

Algorithm

Temporary Sector

Unprotect Mode

Increment

PLSCNT

=25?

Device failed

Yes

Reset

PLSCNT=1

Yes

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

START

PLSCNT=1

Wait 1 us

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

All sectors

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?**

Last sector

verified?

Remove V

from RESET

Write reset

Command

Sector Unprotect

complete

Yes

Set up

next sector

address

Yes

Sector Unprotect

Algorithm

Increment

PLSCNT

PLSCNT=

1000?

Device failed

Yes

Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms

Note: The term "sector" in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns

RESET=V

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

START

PLSCNT=1

555/AA + 2AA/55 +

555/77

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address
with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Data=01h?**

Protect another

sector?

Write reset

command

Sector Protect

complete

Sector Protect

Algorithm

Temporary Sector

Unprotect Mode

Increment

PLSCNT

=25?

Device failed

Yes

Reset

PLSCNT=1

Yes

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

START

PLSCNT=1

Wait 1 us

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

All sectors

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?**

Last sector

verified?

Write reset

Command

Sector Unprotect

complete

Yes

Set up

next sector

address

Yes

Sector Unprotect

Algorithm

Increment

PLSCNT

PLSCNT=

1000?

Device failed

Yes

Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms

Note: The term "sector" in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns

555/AA + 2AA/55 +

555/77

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Hardware Data Protection

The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 12 for command definitions).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.

Low VCC Write Inhibit

When VCC is less than V

LKO

, the device does not accept any

write cycles. This protects data during VCC

power-up and

power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC
is greater than V

LKO

. The system must provide the proper

signals to the control pins to prevent unintentional writes
when VCC

is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

= V

. To initiate a write cycle,

and

must be a logical zero while

is a logical one.

Power-Up Write Inhibit

= V

and

= V

during power up, the

device does not accept commands on the rising edge of

The internal state machine is automatically reset to reading
array data on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
ready to read array data. The system can read CFI
information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Tables 8-11. The system must write the
reset command to return the device to the autoselect mode.

Table 8. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data Description

10h
11h
12h

20h
22h
24h

0051h
0052h
0059h

Query Unique ASCII string "QRY"

13h
14h

26h
28h

0002h
0000h

Primary OEM Command Set

15h
16h

2Ah
2Ch

0040h
0000h

Address for Primary Extended Table

17h
18h

2Eh

30h

0000h
0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

32h
34h

0000h
0000h

Address for Alternate OEM Extended Table (00h = none exists)

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Table 9. System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data Description

1Bh

36h

0027h

VCC Min. (write/erase)

I/O

: volt, I

I/O

: 100 millivolt

1Ch

38h

0036h

VCC Max. (write/erase)

I/O

: volt, I

I/O

: 100 millivolt

1Dh

3Ah

0000h

Vpp Min. voltage (00h = no Vpp pin present)

1Eh

3Ch

0000h

Vpp Max. voltage (00h = no Vpp pin present)

1Fh 3Eh

0003h

Typical timeout per single byte/word write 2

�

20h 40h

0000h

Typical timeout for Min. size buffer write 2

�

s (00h = not supported)

21h

42h

0009h

Typical timeout per individual block erase 2

22h

44h

0000h

Typical timeout for full chip erase 2

ms (00h = not supported)

23h

46h

0005h

Max. timeout for byte/word write 2

times typical

24h

48h

0000h

Max. timeout for buffer write 2

times typical

25h

4Ah

0004h

Max. timeout per individual block erase 2

times typical

26h

4Ch

0000h

Max. timeout for full chip erase 2

times typical (00h = not supported)

Table 10 Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data Description

27h 4Eh

0016h

Device Size = 2

byte

28h
29h

50h
52h

0002h
0000h

Flash Device Interface description

2Ah
2Bh

54h
56h

0000h
0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch 58h

0002h

Number of Erase Block Regions within device

2Dh
2Eh

2Fh
30h

5Ah
5Ch
5Eh

60h

0007h
0000h
0020h
0000h

Erase Block Region 1 Information
(refer to the CFI specification)

31h
32h
33h
34h

62h
64h
66h
68h

003Eh

0000h
0000h
0001h

Erase Block Region 2 Information

35h
36h
37h
38h

6Ah
6Ch
6Eh

70h

0000h
0000h
0000h
0000h

Erase Block Region 3 Information

39h

3Ah
3Bh
3Ch

72h
74h
76h
78h

0000h
0000h
0000h
0000h

Erase Block Region 4 Information

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data Description

40h
41h
42h

80h
82h
84h

0050h
0052h
0049h

Query-unique ASCII string "PRI"

43h

86h

0031h

Major version number, ASCII

44h

88h

0033h

Minor version number, ASCII

45h

8Ah

0000h

Address Sensitive Unlock
0 = Required, 1 = Not Required

46h 8Ch

0002h

Erase

Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh

0001h

Sector

Protect

0 = Not Supported, X = Number of sectors in per group

48h

90h

0001h

Sector Temporary Unprotect
00 = Not Supported, 01 = Supported

49h

92h

0004h

Sector Protect/Unprotect scheme
04 = A29L800 mode

4Ah 94h

00XXh

Number of Sectors (Excluding Bank 1)
XX = 38 (A29DL322)
XX = 30 (A29DL323)
XX = 20 (A29DL324)

4Bh

96h

0000h

Burst Mode Type
00 = Not Supported, 01 = Supported

4Ch

98h

0000h

Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh

9Ah

0085h

ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV

4Eh

9Ch

0095h

ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV

4Fh

9Eh

000Xh

Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot
Device

50h A0h

0000h

Program Suspend
0 = Not Supported, 1 = Supported

57h AEh

0002h

Bank Organization
X = 2 (2 banks, all models)

58h B0h

00XXh

Bank 1 Region Information � Number of Sectors on Bank 1
XX = 0F (A29DL322)
XX = 17 (A29DL323)
XX = 27 (A29DL324)

59h B2h

00XXh

Bank 2 Region Information � Number of Sectors in Bank 2
XX = 38 (A29DL322)
XX = 30 (A29DL323)
XX = 20 (A29DL324)

5Ah

B4h

0000

Bank 3 Region Information � Number of Sector in Bank 3

5Bh

B6h

0000

Bank 4 Region Information � Number of Sector in Bank 4

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences
into the command register initiates device operations. Table
12 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state. A reset command is then required to return the device
to reading array data.
All addresses are latched on the falling edge of

whichever happens later. All data is latched on the rising
edge of

, whichever happens first. Refer to the

AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend-read mode,
after which the system can read data from any non-erase-
suspended sector within the same bank. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if I/O

goes high

during an active program or erase operation, or if the bank is
in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device
Bus Operations section for more information. The Read-Only
Operations table provides the read parameters, and Figure
11 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don't cares for
this command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the bank to which the
system was writing to reading array data. If the program
command sequence is written to a bank that is in the Erase
Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If I/O

goes high during a program or erase operation, writing

the reset command returns the banks to reading array data

(or erase-suspend-read mode if that bank was in Erase
Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system
to access the manufacturer and device codes, and determine
whether or not a sector is protected. Table 12 shows the
address and data requirements. This method is an
alternative to that shown in Table 5, which is intended for
PROM programmers and requires V

on address pin A9.

The autoselect command sequence may be written to an
address wit h in a bank that is either in t he read or erase-
suspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing in
the other bank.
The autoselect command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle that
contains the bank address and the autoselect command. T he
bank then enter s the autoselect mode. The system may read
at any address within the same bank any number of times
without initiating another autoselect command sequence:

A read cycle at address (BA)XX00h (where BA is the bank
address) returns the manufacturer code.

A read cycle at address (BA)XX01h in word mode (or
(BA)XX02h in byte mode) returns the device code.

A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on A7-A0
in word mode (or the address 04h on A6-A-1 in byte mode)
returns 01h if the sector is protected, or 00h if it is
unprotected. (Refer to Tables 3-4 for valid sector
addresses).

The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the bank
was previously in Erase Suspend).

Byte/Word Program Command Sequence

The system may program the device by word or byte,
depending on the state of the

BYTE

pin. Programming is a

four-bus-cycle operation. The program command sequence
is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 12 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, that
bank then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O

, I/O

, or RY/

. Refer

to the Write Operation Status section for information on these
status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from "0" back to a
"1." Attempting to do so may cause that bank to set I/O

= 1,

or cause the I/O

and I/O

status bits to indicate the operation

was successful. However, a succeeding read will show that
the data is still "0." Only erase operations can convert a "0" to
a "1."

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

START

Write Program

Command

Sequence

Data Poll

from System

Verify Data ?

Last Address ?

Programming

Completed

Yes

Increment Address

Embedded

Program

algorithm in

progress

Note : See Table 14 for program command sequnce.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The device
then returns to reading array data.
The device offers accelerated program operations through
the

/ACC pin. When the system asserts V

on the

/ACC pin, the device automatically enters the Unlock

Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the

/ACC pin to accelerate

the operation. Note that the

/ACC pin must not be at V

any operation other than accelerated programming, or device
damage may result. In addition, the

/ACC pin must not

be left floating or unconnected; inconsistent behavior of the
device may result.
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 12
shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O

, I/O

, or RY/

. Refer to the

Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-
out of 50 祍 occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50祍, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additional addresses and commands.
The system can monitor I/O

to determine if the sector erase

timer has timed out (See the section on I/O

: Sector Erase

Timer.). The time-out begins from the rising edge of the final

pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading I/O

, I/O

, or RY/

in the erasing

bank.
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 祍 time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
祍 to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device "erase suspends" all sectors selected
for erasure.) Reading at any address within erase-suspended
sectors produces status information on I/O

璉/O

. The system

can use I/O

, or I/O

and I/O

together, to determine if a

sector is actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O

or I/O

status bits, just as in the standard Byte

Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
To resume the sector erase operation, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is ignored when writing this command.
Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has
resumed erasing.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

Command Definitions

Table 12. A29DL32x Command Definitions

Bus Cycles (Notes 2�5)

First

Second

Third

Fourth

Fifth

Sixth

Command

Sequence

(Note 1)

Cycle Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

XXX

Word 555

2AA

(BA)555

Manufacturer ID

Byte

AAA

555

(BA)AAA

(BA)X00

Word 555

2AA

(BA)555

(BA)X01

Device ID

Byte

AAA

555

(BA)AAA

(BA)X02

(see

Table5)

Word 555

2AA

555

X03

Continuation ID

Byte

AAA

555

AAA

X06

Word 555

2AA

(BA)555

(SA)

Autoselect

(
Note 8

)

Sector Protect Verify
(Note 9)

Byte

AAA

555

(BA)AAA

(SA)X04

00/01

Word 555

2AA

555

Command Temporary
Sector Unprotect (Note15)

Byte

AAA

555

AAA

Word 555

2AA

555

Program

Byte

AAA

555

AAA

A0 PA PD

Word 555

2AA

555

Unlock Bypass

Byte

AAA

555

AAA

Unlock Bypass Program (Note 10)

XXX

Unlock Bypass Reset (Note 11)

XXX

Word 555

2AA

555

2AA

555

Chip Erase

Byte

AAA

555

AAA

AA A

555

AAA

Word 555

2AA

55 555 80 555

2AA

Sector Erase

Byte

AAA

555

AAA AAA

555

55 SA 30

Erase Suspend (Note 12)

XXX

Erase Resume (Note 13)

XXX

Word 55

CFI Query (Note 14)

Byte

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of

pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector.

BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits I/O

-I/O

are don't care in command sequences. Except for RD and PD.

5. Unless otherwise noted, address bits A20-A11 are don't cares.

6. No unlock or command cycles required when bank is reading array data.

7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase

Suspend) when a bank is in the autoselect mode, or if I/O

goes high (while the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain

the manufacture ID, or device ID information. Data bits I/O

-I/O

are don't care. See the Autoselect Command Sequence

section for more information.

9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.

11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation, and require the bank address.

13. The Erase Resume command is valid only during the Erase.

14. Command is valid when device is ready to read array data or when device is in autoselect mode.

15. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase

suspend condition, this command is still effective even a reset command has been applied. The reset command which can

deactivate the software temporary unprotect command is useful only after the erase command is complete.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

WRITE OPERATION STATUS

The device provides several bits to determine the status of a
program or erase operation: I/O

, I/O

, and I/O

Table 13 and the following subsections describe the function
of these bits. I/O

and I/O

each offer a method for

determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/

, to determine whether

an Embedded Program or Erase operation is in progress or
has been completed.

I/O

Data

Polling

The

Data

Polling bit, I/O

, indicates to the host system

whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.

Data

Polling is

valid after the rising edge of the final

pulse in the

program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O

the complement of the datum programmed to I/O

This I/O

status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O

The system must provide the program address to read valid
status information on I/O

. If a program address falls within a

protected sector,

Data

Polling on I/O

is active for

approximately 1

�

s, then the device returns to reading array

data.
During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O

. When the Embedded Erase algorithm

is complete, or if the device enters the Erase Suspend mode,

Data

Polling produces a "1" on I/O

. The system must

provide an address within any of the sectors selected for
erasure to read valid status information on I/O

After an erase command sequence is written, if all sectors
selected for erasing are protected,

Data

Polling on I/O

active for approximately 100

�

s, then the bank returns to

reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O

at an address within a

protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, I/O

may change asynchronously with I/O

�

I/O

while Output Enable (

) is asserted low. That is, the

device may change from providing status information to valid
data on I/O

. Depending on when the system samples the

I/O

output, it may read the status or valid data. Even if the

device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O

-I/O

may be still

invalid. Valid data on I/O

-I/O

will appear on successive read

cycles.
Table 13 shows the outputs for

Data

Polling on I/O

. Figure

5 shows the

Data

Polling algorithm. Figure 19 in the AC

Characteristics section shows the

Data

Polling timing

diagram.

START

Read I/O

-I/O

Address = VA

I/O

= Data ?

FAIL

Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O

should be rechecked even if I/O

= "1" because

I/O

may change simultaneously with I/O

Read I/O

- I/O

Address = VA

I/O

= 1?

I/O

= Data ?

Yes

PASS

Yes

Figure 5. Data Polling Algorithm

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

RY/

: Read/

Busy

The RY/

is a dedicated, open-drain output pin that

indicates whether an Embedded algorithm is in progress or
complete. The RY/

status is valid after the rising edge of

the final

pulse in the command sequence. Since RY/

is an open-drain output, several RY/

pins can be tied

together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 13 shows the outputs for RY/

I/O

: Toggle Bit I

Toggle Bit I on I/O

indicates whether an Embedded Program

or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final

pulse in the command sequence (prior to the

program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O

to toggle.

The system may use either

to control the read

cycles. When the operation is complete, I/O

stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O

toggles for

approximately 100

�

s, then returns to reading array data. If not

all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O

and I/O

together to determine

whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O

toggles. When the device

enters the Erase Suspend mode, I/O

stops toggling.

However, the system must also use I/O

to determine which

sectors are erasing or erase-suspended. Alternatively, the
system can use I/O

(see the subsection on " I/O

Data

Polling").
If a program address falls within a protected sector, I/O

toggles for approximately 1

�

s after the program command

sequence is written, then returns to reading array data.
I/O

also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O

. Figure 6

shows the toggle bit algorithm. Figure 20 in the "AC
Characteristics" section shows the toggle bit timing diagrams.
Figure 23 shows the differences between I/O

and I/O

graphical form. See also the subsection on I/O

: Toggle Bit II.

START

Read I/O

-I/O

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

Note:
The system should recheck the toggle bit even if I/O

because the toggle bit may stop toggling as I/O

changes to

See the subsections on I/O

and I/O

for more information.

Read I/O

- I/O

Twice

I/O

= 1?

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Complete

Read I/O

-I/O

(Notes 1,2)

Figure 6. Toggle Bit Algorithm

(Note 1)

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

I/O

: Toggle Bit II

The "Toggle Bit II" on I/O

, when used with I/O

, indicates

whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final

pulse in the command sequence.

I/O

toggles when the system reads at addresses within those

sectors that have been selected for erasure. (The system may
use either

to control the read cycles.) But I/O

cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O

, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O

and I/O

Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O

: Toggle Bit II" explains the algorithm. See

also the " I/O

: Toggle Bit I" subsection. Figure 20 shows the

toggle bit timing diagram. Figure 21 shows the differences
between I/O

and I/O

in graphical form.

Reading Toggle Bits I/O

, I/O

Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O

-I/O

at least twice in a row to determine whether a toggle

bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O

-I/O

on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O

is high (see the section

on I/O

). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O

went high. If the toggle bit

is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O

has not gone high. The

system may continue to monitor the toggle bit and I/O

through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figure
6).

I/O

: Exceeded Timing Limits

I/O

indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these
conditions I/O

produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully
completed.
The device may output a "1" on I/O

if the system tries to

program a "1" to a location that was previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O

produces a

"1." .
Under both these conditions, the system must write the reset
command to return to reading array data (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).

I/O

: Sector Erase Timer

After writing a sector erase command sequence, the system
may read I/O

to determine whether or not an erase

operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O

switches from "0" to "1." The system may

ignore I/O

if the system can guarantee that the time

between additional sector erase commands will always be
less than 50

�

s. See also the "Sector Erase Command

Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O

(

Data

Polling) or I/O

(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O

. If I/O

is "1", the

internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O

is "0", the device will

accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O

prior to and following each

subsequent sector erase command. If I/O

is high on the

second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O

relative to the other status

bits.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature Plastic Packages. . . -65

�

C to + 150

�

Ambient Temperature with Power Applied. -65

�

C to + 125

�

Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . ....... . -0.5V to +4.0V
A9,

& RESET (Note 2) . . . . . . . . . . . . -0.5V to +12.5V

/ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V

All other pins (Note 1) . . . . . . . . . . .... . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . .... . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. See Figure 7. During
voltage transitions, input or I/O pins may

overshoot to

VCC +2.0V for periods up to 20ns. See Figure 8.

2. Minimum DC input voltage on A9,

, RESET and

/ACC is -0.5V. During voltage transitions, A9,

/ACC and RESET may overshoot VSS to -2.0V for

periods of up to 20ns. See Figure 7. Maximum DC input
voltage on A9 is +12.5V which may overshoot to 14.0V
for periods up to 20ns. Maximum DC input voltage on

/ACC is +9.5V which may overshoot to +12.0V for

period up to 20ns.

3. No more than one output is shorted to ground at a time.

Duration of the short circuit should not be greater than
one second.

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices
Ambient Temperature (T

) . . . . . . . . . . . . . . -40

�

C to +85

�

VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . ......+2.7V to +3.6V

Operating ranges define those limits between which the
functionally of the device is guaranteed.

Figure 7. Maximum Negative Overshoot Waveform

20ns

+0.8V

-0.5V

-2.0V

Figure 8. Maximum Positive Overshoot Waveform

20ns

VCC+0.5V

2.0V

VCC+2.0V

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

Input Load Current

= VSS to VCC. VCC = VCC Max

�

1.0

�

LIT

A9 Input Load Current

VCC = VCC Max, A9 =12.5V

�

Output Leakage Current

OUT

= VSS to VCC. VCC = VCC Max

�

1.0

�

5 MHz

10 16

= V

Byte Mode

1 MHz

2 4

5 MHz

CC1

VCC Active Read Current
(Notes 1, 2)

= V

Word Mode

1 MHz

CC2

VCC Active Write Current
(Notes 2, 3)

= V

30 mA

CC3

VCC Standby Current (Note 2)

= V

RESET

= VCC

�

0.3V

0.2

�

CC4

VCC Reset Current (Note 2)

RESET

= VSS

�

0.3V

0.2 5

�

CC5

Automatic Sleep Mode
(Note 2, 4)

= VCC

�

0.3V; V

= VSS

�

0.3V

0.2 5

�

Byte 21

CC6

VCC Active Read-While-Program
Current (Notes 1, 2)

= V

Word

Byte 21

CC7

VCC Active Read-While-Erase
Current (Notes 1, 2)

= V

Word

CC8

VCC Active
Program-While-Erase-Suspended
Current (Notes 2, 5)

= V

35 mA

ACC pin

ACC

ACC Accelerated Program Current,
Word or Byte

= V

VCC pin

Input Low Level

-0.5

0.8

Input High Level

0.7 x VCC

VCC + 0.3

Voltage for

/ACC Sector

Protect/Unprotect and Program
Acceleration

VCC = 3.0 V � 10%

8.5

9.5

Voltage for Autoselect and
Temporary Unprotect Sector

VCC = 3.0 V � 10%

8.5

12.5

Output Low Voltage

= 4.0mA, VCC = VCC Min

0.45

OH1

= -2.0 mA, VCC = VCC Min

0.85 x VCC

OH2

Output High Voltage

= -100

�

A, VCC = VCC Min

VCC - 0.4

LKO

Low VCC Lock-Out Voltage (Note 5)

2.3

2.5

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with

at V

2. Maximum I

specifications are tested with VCC = VCC max.

3. I

active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30ns. Typical sleep mode current

is 200nA.

5. Not 100% tested.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

AC CHARACTERISTICS

Read Only Operations

Parameter

Speed

JEDEC

Std

Description Test

Setup

-70 -80 -90 -120

Unit

AVAV

Read Cycle Time (Note 1)

Min.

70 80 90 120 ns

AVQV

ACC

Address to Output Delay

= V

Max.

70 80 90 120 ns

ELQV

Chip Enable to Output Delay

= V

Max.

70 80 90 120 ns

GLQV

Output Enable to Output Delay

Max.

30 30 40 50 ns

EHQZ

Chip Enable to Output High Z
(Notes 1,3)

Max.

16 16 16 16 ns

GHQZ

Output Enable to Output High Z
(Notes 1,3)

Max.

16 16 16 16 ns

AXQX

Output Hold Time from Addresses,

, Whichever Occurs First

Min.

0 ns

Read

Min.

OEH

Output

Enable

Hold

Time (Note 1)

Toggle and

Data

Polling

Min.

10 ns

Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from

high to

the data bus driven to VCC/2 is taken as t

Figure 11. Read Operation Timings

Addresses

Addresses Stable

Output Valid

High-Z

Output

OEH

High-Z

ACC

RESET

RY/BY

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed

JEDEC

Std

Description

-70 -80 -90 -120

Unit

AVAV

Write Cycle Time (Note 1)

Min.

70 80 90 120 ns

AVWL

Address Setup Time

Min.

ASO

Address Setup Time to

low during toggle bit

polling

15 15 15 15 ns

WLAX

Address Hold Time

Min.

45 45 45 50 ns

AHT

Address Hold Time From

high during

toggle bit polling

DVWH

Data Setup Time

Min.

35 35 45 50 ns

WHDX

Data Hold Time

Min.

OEPH

Output Enable High during toggle bit polling

Min.

20 20 20 20 ns

GHWL

Read Recover Time Before Write

(

high to

low)

Min.

ELWL

Setup Time

Min.

WHEH

Hold Time

Min.

WLWH

Write Pulse Width

Min.

30 30 35 50 ns

WHDL

WPH

Write Pulse Width High

Min.

30 30 30 30 ns

SR/W

Latency Between Read and Write Operations

Min.

Byte Typ.

WHWH1

Byte Programming Operation
(Note 2)

Word Typ.

�

WHWH1

Accelerated Programming Operation,

Word or Byte (Note 2)

Typ.

4 sec

WHWH2

Sector

Erase

Operation (Note 2)

Typ.

0.7

sec

vcs

VCC Set Up Time (Note 1)

Min.

�

Recovery Time from RY/

Min

BUSY

Program/Erase Valid to RY/

Delay

Min

Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

A29DL32x Series

PRELIMINARY (May, 2005, Version 0.0)

AMIC Technology, Corp.

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ. (Note 1)

Max. (Note 2)

Unit

Comments

Sector Erase Time

0.7

sec

Chip Erase Time

sec

Excludes 00h programming
prior to erasure (Note 4)

Byte Programming Time

150

�

Word Programming Time

210

�

Accelerated Word/Byte Programming Time

120

�

Byte Mode

sec

Chip Programming Time

(Note 3)

Word Mode

sec

Excludes system-level
overhead (Note 5)

Notes:
1. Typical program and erase times assume the following conditions: 25

�

C, 3.0V VCC, 10,000 cycles. Additionally, programming

typically assumes checkerboard pattern.

2. Under worst case conditions of 90

�

C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12

for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 10,000 cycles.

LATCH-UP CHARACTERISTICS

Description Min.

Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V

VCC Current

-100 mA

+100 mA

Input voltage with respect to VSS on all pins except I/O pins
(including A9,

and

RESET

)

-1.0V

12.5V

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.

PACKAGE AND PIN CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

TSOP

7.5

Input

Capacitance

TF BGA

4.2

TSOP

8.5

OUT

Output Capacitance

OUT

TF BGA

5.4

6.5

TSOP

7.5

IN2

Control Pin Capacitance

TF BGA

3.9

4.7

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25

�

C, f = 1.0MHz

DATA RETENTION

Parameter

Test Conditions

Min

Unit

150

�

10 Years

Minimum Pattern Data Retention Time

125

�

20 Years

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: A29DL322UV-80

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: A29DL322UV-80