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A29L004A Series

512K X 8 Bit CMOS 3.0 Volt-only,

Preliminary

Boot Sector Flash Memory

PRELIMINARY

(March, 2005, Version 0.0)

AMIC Technology, Corp.

Document Title
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. History Issue

Date Remark

0.0

Initial issue

March 9, 2005

Preliminary

A29L004A Series

512K X 8 Bit CMOS 3.0 Volt-only,

Preliminary

Boot Sector Flash Memory

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Features

Single power supply operation

- Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

- Regulated voltage range: 3.0 to 3.6 volt read and write

operations for compatibility with high performance 3.3
volt microprocessors

Access times:

70/90

(max.)

Current:

- 4 mA typical active read current
- 20 mA typical program/erase current

200 nA typical CMOS standby

200 nA Automatic Sleep Mode current

Flexible sector architecture

16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows code
changes in previously locked sectors

Unlock Bypass Program Command

- Reduces overall programming time when issuing

multiple program command sequence

Top or bottom boot block configurations available
Embedded Algorithms

- Embedded Erase algorithm will automatically erase the

entire chip or any combination of designated sectors and
verify the erased sectors

- Embedded Program algorithm automatically writes and

verifies data at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

Reliable operation for the life of the system

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-supply

Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion of
program or erase operations

Ready /

BUSY

pin (RY /

)

- Provides a hardware method of detecting completion of

program or erase operations (not available on 32-pin
PLCC & (s)TSOP packages)

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from, or

program data to, a non-erasing sector, then resumes the
erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array
data (not available on 32 pin PLCC & (s)TSOP
packages)

Package options

40-pin TSOP (forward type), 32-pin PLCC or (s)TSOP

(forward type)

General Description

The A29L004A is a 4Mbit, 3.0 volt-only Flash memory
organized as 524,288 bytes of 8 bits. The 8 bits of data
appear on I/O

- I/O

. The A29L004A is offered in 40-pin

TSOP, 32-pin PLCC or (s)TSOP packages. This device is
designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L004A can also be programmed in standard EPROM
programmers.
The A29L004A has the first toggle bit, I/O

, which indicates

whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O

toggle bit, the

A29L004A has a second toggle bit, I/O

, to indicate whether

the addressed sector is being selected for erase. The
A29L004A also offers the ability to program in the Erase
Suspend mode. The standard A29L004A offers access times
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (

), write enable (

)

and output enable (

) controls.

The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.

The A29L004A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.

The host system can detect whether a program or erase
operation is complete by observing the RY /

pin (not

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

available on 32-pin PLCC & (s)TSOP), or

by reading the I/O

(

Data

Polling) and I/O

(toggle) status bits. After a program

or erase cycle has been completed, the device is ready to
read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L004A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the

sectors of memory. This can be achieved via programming
equipment.

The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,

or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data (not available on 32-pin PLCC & (s)TSOP). The

RESET pin may be tied to the system reset circuitry. A

system reset would thus also reset the device, enabling the
system microprocessor to read the boot-up firmware from the
Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.

Pin Configurations

40-pin TSOP

A29L004AW

A15
A14
A13
A12
A11

A9
A8

RESET

RY/BY

A18

A7
A6
A5

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

I/O

VCC

I/O

A10

VSS

A17

A16

I/O

23
22
21

VSS

A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PLCC

32-pin TSOP (8mm X 20mm)

32-pin sTSOP (8mm X 13.4mm)

32-pin sTSOP (8mm X 14mm)

A29L004AV (8mm X 20mm)
A29L004AX (8mm X 13.4mm)

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15
16

A9
A8

A13
A14
A17

VCC

A16

A15

A12

A7
A6
A5
A4

32
31
30
29
28
27
26
25
24
23
22
21

20
19
18
17

I/O

GND

I/O

A10

A11

A18

A29L004AL

I/O

A13

A14

A12

A15

A16

A18

A17

I/
O

GND

I/
O

A11

OE
A10

I/
O

A29L004AY (8mm X 14mm)

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Block Diagram

Pin Descriptions

Pin No.

Description

A0 - A18

Address Inputs

I/O

- I/O

Data

Inputs/Outputs

Chip Enable

Write Enable

Output Enable

RESET

Hardware Reset (N/A 32-pin PLCC, (s)TSOP)

RY/

Ready/

BUSY

- Output (N/A 32-pin PLCC, (s)TSOP)

VSS Ground

VCC Power

Supply

Pin not connected internally

State

Control

Command

ddres

s
Latc

X-decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Cell Matrix

Y-Gating

VCC Detector

PGM Voltage

Generator

Data Latch

Input/Output

Buffers

Erase Voltage

Generator

VCC

VSS

CE
OE

A0-A18

I/O

- I/O

Timer

STB

RESET

Sector Switches

RY/BY (N/A 32-pin PLCC, (s)TSOP)

(N/A 32-pin PLCC,

(s)TSOP)

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Absolute Maximum Ratings*

Storage Temperature Plastic Packages . ...... .0

C to + 70

Ambient Temperature with Power Applied...... 0

C to + 70

Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . ...... . . . -0.5V to +4.0V
A9,

& RESET (Note 2) . . . . . . . . . . ..... . -0.5 to +12.5V

All other pins (Note 1) . . . . . . . . . . . ..... -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . ..... ... 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may

overshoot to VCC +2.0V

for periods up to 20ns.

2. Minimum DC input voltage on A9,

and RESET is -

0.5V. During voltage transitions, A9,

and RESET

may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns. ( RESET is
N/A on 32-pin PLCC & (s)TSOP)

3. No more than one output is shorted at a time. Duration of

the short circuit should not be greater than one second.

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.

Operating Ranges

Commercial (C) Devices
Ambient Temperature (T

) . . . . . . . ..... . . . . . . 0

C to +70

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . ..... . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the

command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.

Table 1. A29L004A Device Bus Operations

Operation

RESET

(N/A 32-pin PLCC, (s)TSOP)

A0 A18

I/O

- I/O

Read L

H A

OUT

Write L

H A

CMOS Standby

VCC

0.3 V

X X

VCC

0.3 V

X High-Z

Output Disable

High-Z

Hardware Reset

High-Z

Sector Protect
(See Note 2)

L H

Sector

Address,

A6=L, A1=H, A0=L

Sector Unprotect
(See Note 2)

L H

Sector

Address,

A6=H, A1=H, A0=L

Temporary Sector
Unprotect

X X

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Notes:

1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

2. This function is not available on 32-pin PLCC & (s)TSOP packages.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the

and

pins to V

is the power control and selects

the device.

is the output control and gates array data to

the output pins.

should remain at V

all the time during

read operation. The internal state machine is set for reading
array data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content
occurs during the power transition. No command is necessary
in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address
inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command
register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
l

CC1

in the DC Characteristics table represents the active

current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive

and

to V

, and

to V

. The device features an Unlock Bypass mode to

facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a byte, instead of four.
The "Byte Program Command Sequence" section has details
on programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O

- I/O

. Standard read

cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
I

CC2

in the DC Characteristics table represents the active

current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O

I/O

. Standard read cycle timings and I

read specifications

apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

RESET pins (

only on 32-pin PLCC & (s)TSOP

packages) are both held at VCC

0.3V. (Note that this is a

more restricted voltage range than V

.) If

and RESET

(N/A on 32-pin PLCC & (s)TSOP packages) are held at V

but not within VCC

0.3V, the device will be in the standby

mode, but the standby current will be greater. The device
requires the standard access time (t

) before it is ready to

read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
I

CC3

and

CC4

in the DC Characteristics tables represent the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t

ACC

+30ns. The automatic

sleep mode is independent of the

and

control

signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. I

CC4

in the

DC Characteristics table represents the automatic sleep mode
current specification.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance
state.

RESET

: Hardware Reset Pin (N/A on 32-pin PLCC &

(s)TSOP packages)

The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the

RESET pin low for at least a period of t

, the device

immediately terminates any operation in progress, tristates all
data output pins, and ignores all read/write attempts for the
duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS

0.3V, the device draws CMOS

standby current (I

CC4

). If RESET is held at V

but not within

VSS

0.3V, the standby current will be greater.

The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/

pin remains a "0" (busy) until the internal reset

operation is complete, which requires a time t

READY

(during

Embedded Algorithms). The system can thus monitor RY/

to determine whether the reset operation is complete. If

RESET is asserted when a program or erase operation is not

executing (RY/

pin is "1"), the reset operation is completed

within a time of t

READY

(not during Embedded Algorithms). The

system can read data t

after the RESET pin return to V

Refer to the AC Characteristics tables for RESET parameters
and diagram.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Table 2. A29L004A Top Boot Block Sector Address Table

Sector

A18 A17 A16 A15 A14 A13

Sector

Size

(Kbytes)

Address Range

(in hexadecimal)

SA0

00000h - 0FFFFh

SA1

10000h - 1FFFFh

SA2

20000h - 2FFFFh

SA3

30000h - 3FFFFh

SA4

40000h - 4FFFFh

SA5

50000h - 5FFFFh

SA6

60000h - 6FFFFh

SA7

70000h - 77FFFh

SA8

1 1 1 1 0 0 8 78000h

79FFFh

SA9

1 1 1 1 0 1 8 7A000h

7BFFFh

SA10

1 1 1 1 1 X 16 7C000h

7FFFFh

Table 3. A29L004A Bottom Boot Block Sector Address Table

Sector

A18 A17 A16 A15 A14 A13

Sector

Size

(Kbytes)

Address Range

(in hexadecimal)

SA0

0 0 0 0 0 X 16 00000h

03FFFh

SA1

0 0

0 0 1 0 8 04000h

05FFFh

SA2

0 0 0 0 1 1 8 06000h

07FFFh

SA3

0 0 0 1 X X 32 08000h

0FFFFh

SA4

10000h - 1FFFFh

SA5

20000h - 2FFFFh

SA6

30000h - 3FFFFh

SA7

40000h - 4FFFFh

SA8

50000h - 5FFFFh

SA9

60000h - 6FFFFh

SA10

70000h - 7FFFFh

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Autoselect Mode

The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O

- I/O

. This mode is primarily

intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires V

(11.5V to 12.5 V) on address pin A9. Address

pins A6, A1, and A0 must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when
verifying sector protection, the sector address must appear

on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O

- I/O

.To access the

autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require V

. See "Command Definitions" for details on using

the autoselect mode.

Table 4. A29L004A Autoselect Codes (High Voltage Method)

Description

A18

A13

A12

A10

A1 A0

I/O

Manufacturer ID: AMIC

X L X L L

37h

Device ID: A29L004A

(Top Boot Block)

L L H X X V

X L X L H

34h

Device ID: A29L004A

(Bottom Boot Block)

L L H X X V

X L X L H

B5h

Continuation ID

X L X H H

7Fh

01h

(protected)

Sector Protection Verification

X L X H L

00h

(unprotected)

L=Logic Low= V

, H=Logic High=V

, SA=Sector Address, X=Don't Care.

Note: The autoselect codes may also be accessed in-system via command sequences.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the

RESET pin only (N/A on 32-pin PLCC & (s)TSOP packages),

and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithm and
the Sector Protect / Unprotect Timing Diagram illustrates the
timing waveforms for this feature. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the first
sector unprotect write cycle. The alternate method must be
implemented using programming equipment. The procedure
requires a high voltage (V

) on address pin A9 and the

control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V

power-up transitions, or from system noise. The device

is powered up to read array data to avoid accidentally writing
data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

= V

. To initiate a write cycle,

and

must be a logical zero while

is a logical one.

Power-Up Write Inhibit

= V

and

= V

during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

Temporary Sector Unprotect (N/A on 32-pin PLCC
& (s)TSOP packages)

This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to V

During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once V

is removed from the RESET pin, all the previously

protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.

START

RESET = V

(Note 1)

Perform Erase or

Program Operations

RESET = V

Temporary Sector

Unprotect

Completed (Note 2)

Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

START

PLSCNT=1

RESET=V

Wait 1 us

First Write

Cycle=60h?

Set up sector

address

Sector Protect

Write 60h to sector

address with A6=0,

A1=1, A0=0

Wait 150 us

Verify Sector

Protect: Write 40h

to sector address
with A6=0, A1=1,

A0=0

Read from

sector address

with A6=0,

A1=1, A0=0

Data=01h?

Protect another

sector?

Remove V

from RESET

Write reset

command

Sector Protect

complete

Sector Protect

Algorithm

Temporary Sector

Unprotect Mode

Increment

PLSCNT

=25?

Device failed

Yes

Reset

PLSCNT=1

Yes

Protect all sectors:

The indicated portion of

the sector protect

algorithm must be

performed for all

unprotected sectors prior

to issuing the first sector

unprotect address

START

PLSCNT=1

RESET=V

Wait 1 us

First Write

Cycle=60h?

Temporary Sector

Unprotect Mode

Yes

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with A6=1,

A1=1, A0=0

Wait 15 ms

Verify Sector

Unprotect : Write

40h to sector

address with A6=1,

A1=1, A0=0

Read from sector

address with A6=1,

A1=1, A0=0

Data=00h?

Last sector

verified?

Remove V

from RESET

Write reset

Command

Sector Unprotect

complete

Yes

Set up

next sector

address

Yes

Sector Unprotect

Algorithm

Increment

PLSCNT

PLSCNT=

1000?

Device failed

Yes

Figure 2. In-System Sector Protect/Unprotect Algorithms

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Command Definitions

Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of

whichever happens later. All data is latched on the rising
edge of

, whichever happens first. Refer to the

appropriate timing diagrams in the "AC Characteristics"
section.

Reading Array Data

The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O

goes high, or while in the

autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O

goes high during a program or erase operation, writing

the reset command returns the device to reading array data
(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires V

on address bit A9.

The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. Table 5 shows the
address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O

, I/O

, or RY/BY (N/A on 32-

pin PLCC & (s)TSOP packages). See "Write Operation
Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a "0" back to a
"1". Attempting to do so may halt the operation and set I/O5 to
"1", or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still "0". Only erase operations can
convert a "0" to a "1".

A29L004A Series

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AMIC Technology, Corp.

START

Write Program

Command

Sequence

Data Poll

from System

Verify Data ?

Last Address ?

Programming

Completed

Yes

Increment Address

Embedded

Program

algorithm in

progress

Note : See the appropriate Command Definitions table for
program command sequence.

Figure 3. Program Operation

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 5
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data

00h. Addresses are don't care for both cycle. The device
returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in "AC Characteristics" for
parameters, and to Program Operation Timings for timing
diagrams.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O

, I/O

, or I/O

. See

"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50

s begins. During the time-out period, additional

sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50

s, otherwise the last address and command

might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50

s, the

system need not monitor I/O

. Any command other than

Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.

A29L004A Series

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START

Write Erase

Command

Sequence

Data Poll

from System

Data = FFh ?

Erasure Completed

Yes

Embedded
Erase
algorithm in
progress

Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O

: Sector Erase Timer" for more information.

Figure 4. Erase Operation

The system can monitor I/O

to determine if the sector erase

timer has timed out. (See the " I/O

: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

pulse in the command sequence.

Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O

, I/O

, or I/O

. Refer to "Write

Operation Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50

s time-out period during the sector erase

command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20

s to suspend the erase operation. However, when the

Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O

- I/O

. The system can use I/O

, or I/O

and I/O

together, to

determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O

or I/O

status bits, just

as in the standard program operation. See "Write Operation
Status" for more information.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.

A29L004A Series

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AMIC Technology, Corp.

Table 5. A29L004A Command Definitions

Bus Cycles (Notes 2 - 5)

First Second Third Fourth Fifth Sixth

Command Sequence

(Note 1)

Cycle

Addr Data Addr Data

Addr Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

XXX

Manufacturer ID

555 AA

2AA

555

X00

Device ID,
Top Boot Block

4 555

2AA

55 555

X01

Device ID,
Bottom Boot Block

4 555

2AA

555

X01

Continuation ID

555

2AA

555

X03

XX00

Autoselect (Note 8)

Sector Protect Verify
(Note 9)

4 555

2AA

55 555

(SA)

X02 XX01

Program 4

555

2AA

555

Unlock

Bypass

555

2AA

55 555

Unlock Bypass Program (Note 10)

XXX A0

Unlock Bypass Reset (Note 11)

XXX 90

XXX

Chip Erase

555

2AA

555

2AA 55

555

Sector Erase

555

2AA

555

2AA 55

Erase Suspend (Note 12)

XXX

Erase Resume (Note 13)

XXX

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the

pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of

pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A13 select a unique sector.

Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O

goes high

(while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more

information.

9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass

mode.

11. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
12. The Erase Resume command is valid only during the Erase Suspend mode.

A29L004A Series

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Write Operation Status

Several bits, I/O

, I/O

RY/

are provided in

the A29L004A to determine the status of a write operation
(RY/

pin is not available on 32-pin PLCC & (s)TSOP

packages). Table 6 and the following subsections describe
the functions of these status bits. I/O

, I/O

and RY/

each

offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.

I/O

Data

Polling

The

Data

Polling bit, I/O

, indicates to the host system

whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.

Data

Polling is

valid after the rising edge of the final

pulse in the

program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O

the complement of the datum programmed to I/O

This I/O

status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O

The system must provide the program address to read valid
status information on I/O

. If a program address falls within a

protected sector,

Data

Polling on I/O

is active for

approximately 2

s, then the device returns to reading array

data.
During the Embedded Erase algorithm,

Data

Polling

produces a "0" on I/O

. When the Embedded Erase algorithm

is complete, or if the device enters the Erase Suspend mode,

Data

Polling produces a "1" on I/O

.This is analogous to the

complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O

After an erase command sequence is written, if all sectors
selected for erasing are protected,

Data

Polling on I/O

active for approximately 100

s, then the device returns to

reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O

has changed from the

complement to true data, it can read valid data at I/O

- I/O

on the following read cycles. This is because I/O

may

change asynchronously with I/O

- I/O

while Output Enable

(

) is asserted low. The

Data

Polling Timings (During

Embedded Algorithms) in the "AC Characteristics" section
illustrates this. Table 6 shows the outputs for

Data

Polling

on I/O

. Figure 5 shows the

Data

Polling algorithm.

START

Read I/O

-I/O

Address = VA

I/O

= Data ?

FAIL

Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O

should be rechecked even if I/O

= "1" because

I/O

may change simultaneously with I/O

Read I/O

- I/O

Address = VA

I/O

= 1?

I/O

= Data ?

Yes

PASS

Yes

Figure 5. Data Polling Algorithm

A29L004A Series

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RY/

: Read/

Busy

(N/A on 32-pin PLCC & (s)TSOP

packages)

The RY/

is a dedicated, open-drain output pin that

indicates whether an Embedded algorithm is in progress or
complete. The RY/

status is valid after the rising edge of

the final

pulse in the command sequence. Since

RY/

is an open-drain output, several RY/

pins can be

tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 6 shows the outputs for RY/

. Refer to "

RESET

Timings", "Timing Waveforms for Program Operation" and
"Timing Waveforms for Chip/Sector Erase Operation" for
more information.

I/O

: Toggle Bit I

Toggle Bit I on I/O

indicates whether an Embedded Program

or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final

pulse in the command sequence (prior to the

program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O

to toggle.

(The system may use either

to control the read

cycles.) When the operation is complete, I/O

stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O

toggles for

approximately 100

s, then returns to reading array data. If

not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O

and I/O

together to determine

whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O

toggles. When the

device enters the Erase Suspend mode, I/O

stops toggling.

However, the system must also use I/O

to determine which

sectors are erasing or erase-suspended. Alternatively, the
system can use I/O

(see the subsection on " I/O

Data

Polling").
If a program address falls within a protected sector, I/O

toggles for approximately 2

s after the program command

sequence is written, then returns to reading array data.
I/O

also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O

. Refer to Figure 6 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O

vs.

I/O

figure shows the differences between I/O

and I/O

graphical form. See also the subsection on " I/O

: Toggle Bit II".

I/O

: Toggle Bit II

The "Toggle Bit II" on I/O

, when used with I/O

, indicates

whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final

pulse in the command sequence.

I/O

toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The
system may use either

to control the read

cycles.) But I/O

cannot distinguish whether the sector is

actively erasing or is erase-suspended. I/O

, by comparison,

indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs for
I/O

and I/O

Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O

: Toggle Bit II" explains the algorithm. See

also the " I/O

: Toggle Bit I" subsection. Refer to the Toggle

Bit Timings figure for the toggle bit timing diagram. The I/O

vs. I/O

figure shows the differences between I/O

and I/O

graphical form.

Reading Toggle Bits I/O

, I/O

Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O

- I/O

at least twice in a row to determine whether a

toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O

- I/O

on the following

read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O

is high (see the section

on I/O

). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O

went high. If the toggle bit

is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the
system must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O

has not gone high. The

system may continue to monitor the toggle bit and I/O

through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).

I/O

: Exceeded Timing Limits

I/O

indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these
conditions I/O

produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully
completed.
The I/O

failure condition may appear if the system tries to

program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O

produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array data.

A29L004A Series

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I/O

: Sector Erase Timer

After writing a sector erase command sequence, the system
may read I/O

to determine whether or not an erase

operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out
is complete, I/O

switches from "0" to "1." The system may

ignore I/O

if the system can guarantee that the time

between additional sector erase commands will always be
less than 50

s. See also the "Sector Erase Command

Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O

(

Data

Polling) or I/O

(Toggle Bit I) to ensure the device has accepted the
command sequence, and then read I/O

. If I/O

is "1", the

internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O

is "0", the device will

accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O

prior to and following each

subsequent sector erase command. If I/O

is high on the

second status check, the last command might not have been
accepted. Table 6 shows the outputs for I/O

START

Read I/O

-I/O

Toggle Bit

= Toggle ?

Program/Erase

Operation Not

Commplete, Write

Reset Command

Yes

Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O

changes to "1". See text.

Read I/O

- I/O

Twice

I/O

= 1?

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Complete

Read I/O

-I/O

(Notes 1,2)

Figure 6. Toggle Bit Algorithm

(Note 1)

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Table 6. Write Operation Status

I/O

RY/

Operation

(Note 1)

(Note 2)

(Note 1)

(N/A on 32-pin PLCC

& (s)TSOP packages)

Embedded Program Algorithm

I/O

Toggle

0 N/A

toggle

Standard
Mode

Embedded Erase Algorithm

Toggle

Reading within Erase
Suspended Sector

toggle

0 N/A

Toggle

Reading within Non-Erase
Suspended Sector

Data Data Data Data

Data

Erase
Suspend
Mode

Erase-Suspend-Program

I/O

Toggle

0 N/A

N/A

Notes:
1. I/O

and I/O

require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. I/O

switches to "1" when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See "I/O

: Exceeded Timing Limits" for more information.

Maximum Negative Input Overshoot

20ns

+0.8V

-0.5V

-2.0V

Maximum Positive Input Overshoot

20ns

VCC+0.5V

2.0V

VCC+2.0V

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

DC Characteristics

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min.

Typ.

Max.

Unit

Input Load Current

= VSS to VCC. VCC = VCC Max

1.0

LIT

A9 Input Load Current

VCC = VCC Max, A9 =12.5V

Output Leakage Current

OUT

= VSS to VCC. VCC = VCC Max

1.0

5 MHz

4 10

CC1

VCC Active Read Current
(Notes 1, 2)

= V

1 MHz

2 4

CC2

VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)

= V

30 mA

CC3

VCC Standby Current (Note 2)

= V

RESET

= VCC

0.3V

CC4

VCC Standby Current During Reset
(Note 2) (N/A on 32-pin PLCC &
(s)TSOP packages)

RESET

= VSS

0.3V

1 5

CC5

Automatic Sleep Mode
(Note 2, 4, 5)

= VCC

0.3V; V

= VSS

0.3V

1 5

Input Low Level

-0.5

0.8

Input High Level

0.7 x VCC

VCC + 0.3

Voltage for Autoselect and
Temporary Unprotect Sector

VCC = 3.3 V

11.5

12.5

Output Low Voltage

= 4.0mA, VCC = VCC Min

0.45

OH1

= -2.0 mA, VCC = VCC Min

0.85 x VCC

OH2

Output High Voltage

= -100

A, VCC = VCC Min

VCC - 0.4

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with

at V

. Typical VCC is 3.0V.

2. Maximum I

specifications are tested with VCC = VCC max.

3. I

active while Embedded Algorithm (program or erase) is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30ns. Typical sleep mode current

is 1

5. Not 100% tested.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

DC Characteristics (continued)

Zero Power Flash

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Supply Current in mA

Note: Addresses are switching at 1MHz

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

Frequency in MHz

Supply Current in mA

Note

Typical I

CC1

vs. Frequency

3.6V

2.7V

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

AC Characteristics

Read Only Operations

Parameter Symbols

Speed

JEDEC

Std

Description Test

Setup

-70

-90

Unit

AVAV

Read Cycle Time (Note 1)

Min.

AVQV

ACC

Address to Output Delay

= V

Max.

ELQV

Chip Enable to Output Delay

= V

Max.

GLQV

Output Enable to Output Delay

Max.

Read

Min.

OEH

Output Enable Hold
Time (Note 1)

Toggle and

Data

Polling

Min. 10 10

EHQZ

Chip Enable to Output High Z
(Notes 1)

Max. 25 30 ns

GHQZ

Output Enable to Output High Z
(Notes 1)

25 30

AXQX

Output Hold Time from Addresses,

, Whichever Occurs First

(Note 1)

Min. 0

0 ns

Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.

Timing Waveforms for Read Only Operation

Addresses

Addresses Stable

Output Valid

High-Z

Output

OEH

High-Z

ACC

RESET

RY/BY

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

AC Characteristics

Hardware Reset (

RESET

N/A on 32-pin PLCC & (s)TSOP packages)

Parameter

JEDEC Std

Description

Test Setup

All Speed Options

Unit

READY

RESET

Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

Max

READY

RESET

Pin Low (Not During Embedded

Algorithms) to Read or Write (See Note)

Max

500 ns

RESET

Pulse Width

Min 500 ns

RESET

High Time Before Read (See Note)

Min 50 ns

RY/

Recovery Time

Min 0 ns

RPD

RESET

Low to Standby Mode

Min 20

Note: Not 100% tested.

RESET

Timings

CE, OE

RESET

Ready

Reset Timings NOT during Embedded Algorithms

RESET

Reset Timings during Embedded Algorithms

RY/BY

~ ~

Ready

CE, OE

RY/BY

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Temporary Sector Unprotect (N/A on 32-pin PLCC & (s)TSOP packages)

Parameter

JEDEC Std

Description

All Speed Options

Unit

VIDR

Rise and Fall Time (See Note)

Min

500

RSP

RESET

Setup Time for Temporary Sector

Unprotect

Min 4

Note: Not 100% tested.

Temporary Sector Unprotect Timing Diagram

Program or Erase Command Sequence

RESET

12V

0 or 3V

VIDR

0 or 3V

RSP

RY/BY

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

AC Characteristics

Erase and Program Operations

Parameter

Speed

JEDEC

Std

Description

-70

-90

Unit

AVAV

Write Cycle Time (Note 1)

Min.

AVWL

Address

Setup

Time

Min.

WLAX

Address

Hold

Time

Min.

DVWH

Data Setup Time

Min.

WHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

GHWL

Read Recover Time Before Write

(

high to

low)

Min. 0 ns

ELWL

Setup Time

Min. 0 ns

WHEH

Hold Time

Min. 0 ns

WLWH

Write Pulse Width

Min.

WHWL

WPH

Write Pulse Width High

Min.

WHWH1

Byte Programming Operation

(Note 2)

Typ. 17

WHWH2

Sector

Erase

Operation (Note 2)

Typ.

sec

vcs

VCC Set Up Time (Note 1)

Min.

Recovery Time from RY/

(N/A on 32-pin PLCC & (s)TSOP packages)

Min 0 ns

BUSY

Program/Erase Valid to RY/

Delay

(N/A on 32-pin PLCC & (s)TSOP packages)

Min 90 ns

Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Timing Waveforms for Program Operation

Addresses

Data

VCC

A0h

Program Command Sequence (last two cycles)

OUT

~ ~

Status

~ ~

VCS

Read Status Data (last two cycles)

555h

WHWH1

WPH

Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.

~ ~

BUSY

RY/BY

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Addresses

Data

VCC

55h

30h

Erase Command Sequence (last two cycles)

Complete

~ ~

Progress

~ ~

VCS

Read Status Data

2AAh

WHWH2

WPH

Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.

555h for chip erase

10h for chip erase

~ ~

BUSY

RY/BY

Timing Waveforms for Chip/Sector Erase Operation

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Timing Waveforms for

Data

Polling (During Embedded Algorithms)

Timing Waveforms for Toggle Bit (During Embedded Algorithms)

Note: VA = Valid Address; not required for I/O

. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Addresses

I/O

~ ~

~ ~
~ ~

~ ~

Complement

~ ~

Complement

True

Valid Data

High-Z

Status Data

~ ~

Status Data

True

Valid Data

High-Z

I/O

- I/O

OEH

Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

~ ~

BUSY

RY/BY

High-Z

Addresses

I/O

, I/O

~ ~

~ ~
~ ~

Valid Status

OEH

Valid Status

Valid Data

~ ~

(first read)

(second read)

(stop togging)

RY/BY

~ ~

BUSY

High-Z

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Timing Waveforms for Sector Protect/Unprotect

Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0

~ ~

RESET

SA, A6,

A1, A0

Data

Valid*

60h

40h

Status

Sector Protect/Unprotect

Verify

1us

Sector Protect:150us

Sector Unprotect:15ms

Timing Waveforms for I/O

vs. I/O

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

I/O

Erase

Erase Suspend

Read

Erase Suspend

Read

Erase

Complete

I/O

and I/O

toggle with OE and CE

Note : Both I/O

and I/O

toggle with OE or CE. See the text on I/O

and I/O

in the section "Write Operation Status" for

more information.

~ ~

Erase

Suspend

Program

~ ~

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

AC Characteristics

Erase and Program Operations

Alternate

Controlled Writes

Parameter

Speed

JEDEC Std

Description

-70 -90

Unit

AVAV

Write Cycle Time (Note 1)

Min.

AVEL

Address

Setup

Time

Min.

ELAX

Address

Hold

Time

Min.

DVEH

Data Setup Time

Min.

EHDX

Data Hold Time

Min.

OES

Output Enable Setup Time

Min.

GHEL

Read Recover Time Before Write

(

High to

Low)

Min. 0 ns

WLEL

Setup Time

Min. 0 ns

EHWH

Hold Time

Min. 0 ns

ELEH

Pulse Width

Min. 35 35 ns

EHEL

CPH

Pulse Width High

Min. 30 ns

WHWH1

Byte Programming Operation (Note 2)

Typ.

WHWH2

Sector

Erase

Operation (Note 2)

Typ.

sec

Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Timing Waveforms for Alternate

Controlled Write Operation

Addresses

Data

555 for program

2AA for erase

OUT

~ ~

I/O

~ ~

Data Polling

Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O

= Complement of Data Input, D

OUT

= Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

PD for program
30 for sector erase 10
for chip erase

~ ~

BUSY

WHWH1 or 2

CPH

PA for program
SA for sector erase
555 for chip erase

A0 for program
55 for erase

~ ~

RESET

RY/BY

Erase and Programming Performance

Parameter

Typ. (Note 1)

Max. (Note 2)

Unit

Comments

Sector Erase Time

sec

Chip Erase Time

sec

Excludes 00h programming
prior to erasure

Byte Programming Time

200

Chip Programming Time (Note 3)

13.5

sec

Excludes system-level
overhead (Note 5)

Notes:
1. Typical program and erase times assume the following conditions: 25

C, 3.0V VCC, 10,000 cycles. Additionally, programming

typically assumes checkerboard pattern.

2. Under worst case conditions of 90

C, VCC = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O

= 1. See the section on I/O

for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Latch-up Characteristics

Description Min.

Max.

Input Voltage with respect to VSS on all I/O pins

-1.0V

VCC+1.0V

VCC Current

-100 mA

+100 mA

Input voltage with respect to VSS on all pins except I/O pins
(including A9,

and

RESET

)

-1.0V

12.5V

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.

TSOP Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

Input

Capacitance

7.5

OUT

Output Capacitance

OUT

8.5

IN2

Control Pin Capacitance

7.5

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25

C, f = 1.0MHz

PLCC Pin Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ.

Max. Unit

Input Capacitance

OUT

Output Capacitance

OUT

IN2

Control Pin Capacitance

Notes:
1. Sampled, not 100% tested.
2. Test

conditions

= 25

C, f = 1.0MHz

Data Retention

Parameter

Test Conditions

Min

Unit

150

10 Years

Minimum Pattern Data Retention Time

125

20 Years

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Test Conditions

Test Specifications

Test Condition

-70

-90

Unit

Output Load

1 TTL gate

Output Load Capacitance, C

(including jig capacitance)

100

Input Rise and Fall Times

Input Pulse Levels

0.0 - 3.0

Input timing measurement reference levels

1.5

Output timing measurement reference levels

1.5

Test Setup

6.2 K

Device

Under

Test

Diodes = IN3064 or Equivalent

2.7 K

3.3 V

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Ordering Information
Top Boot Sector Flash

Part No.

Access Time

(ns)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (

Package

A29L004ATL-70

32-pin PLCC

A29L004ATL-70F

32-Pin Pb-Free PLCC

A29L004ATX-70

32-pin sTSOP

(8mm X 13.4mm)

A29L004ATX-70F

32-Pin Pb-Free sTSOP

(8mm X 13.4mm)

A29L004ATV-70

32-pin TSOP

(8mm X 20mm)

A29L004ATV-70F

32-pin Pb-Free TSOP

(8mm X 20mm)

A29L004ATW-70

40-pin TSOP

A29L004ATW-70F

40-pin Pb-Free TSOP

A29L004ATY-70

32-pin sTSOP

(8mm X 14mm)

A29L004ATY-70F

70 4 20 0.2

32-Pin Pb-Free sTSOP

(8mm X 14mm)

A29L004ATL-90

32-pin PLCC

A29L004ATL-90F

32-pin Pb-Free PLCC

A29L004ATX-90

32-pin sTSOP

(8mm X 13.4mm)

A29L004ATX-90F

32-pin Pb-Free sTSOP

(8mm X 13.4mm)

A29L004ATV-90

32-pin TSOP

(8mm X 20mm)

A29L004ATV-90F

32-pin Pb-Free TSOP

(8mm X 20mm)

A29L004ATW-90

40-pin TSOP

A29L004ATW-90F

40-pin Pb-Free TSOP

A29L004ATY-90

32-pin sTSOP

(8mm X 14mm)

A29L004ATY-90F

90 4 20 0.2

32-Pin Pb-Free sTSOP

(8mm X 14mm)

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Bottom Boot Sector Flash

Part No.

Access Time

(ns)

Active Read

Current

Typ. (mA)

Program/Erase

Current

Typ. (mA)

Standby Current

Typ. (

Package

A29L004AUL-70

32-pin PLCC

A29L004AUL-70F

32-pin Pb-Free PLCC

A29L004AUX-70

32-pin sTSOP

(8mm X 13.4mm)

A29L004AUX-70F

32-pin Pb-Free sTSOP

(8mm X 13.4mm)

A29L004AUV-70

32-pin TSOP

(8mm X 20mm)

A29L004AUV-70F

32-pin Pb-Free TSOP

(8mm X 20mm)

A29L004AUW-70

40-pin TSOP

A29L004AUW-70F

40-pin Pb-Free TSOP

A29L004AUY-70

32-pin sTSOP

(8mm X 14mm)

A29L004AUY-70F

70 4 20 0.2

32-Pin Pb-Free sTSOP

(8mm X 14mm)

A29L004AUL-90

32-pin PLCC

A29L004AUL-90F

32-pin Pb-Free PLCC

A29L004AUX-90

32-pin sTSOP

(8mm X 13.4mm)

A29L004AUX-90F

32-pin Pb-Free sTSOP

(8mm X 13.4mm)

A29L004AUV-90

32-pin TSOP

(8mm X 13.4mm)

A29L004AUV-90F

32-pin Pb-Free TSOP

(8mm X 13.4mm)

A29L004AUW-90

40-pin TSOP

A29L004AUW-90F

40-pin Pb-Free TSOP

A29L004AUY-90

32-pin sTSOP

(8mm X 14mm)

A29L004AUY-90F

90 4 20 0.2

32-Pin Pb-Free sTSOP

(8mm X 14mm)

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Package Information

TSOP 40L TYPE I (10 X 20mm) Outline Dimensions

unit: inches/mm

Detail "A"

Gage Plane

0.25

0.076

Pin1

Seating Plane

Dimensions in inches

Dimensions in mm

Symbol

Min Nom

Max Min Nom

Max

- -

0.047

- -

1.20

0.002

- 0.006

0.05

- 0.15

0.037

0.039

0.041

0.95

1.00

1.05

b 0.0067

0.0087

0.0106

0.17

0.22

0.27

c 0.004

0.0083

0.10 - 0.21

0.394 BSC

10.00 BSC

0.020 BSC

0.50 BSC

0.787 BSC

20.00 BSC

0.724 BSC

18.40 BSC

L 0.020

0.024

0.028

0.50

0.60

0.70

Notes:
1. Dimension D

and E do not include mold flash.

2. The lead width dimension does not include dambar protrusion.

Total in excess of the lead width dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Package Information

PLCC 32L Outline Dimension

unit: inches/mm

Dimensions in inches

Dimensions in mm

Symbol

Min Nom

Max Min Nom

Max

A -

0.134

3.40

0.0185

- - 0.47

- -

0.105

0.110

0.115

2.67

2.80

2.93

0.026

0.028

0.032

0.66

0.71

0.81

b 0.016

0.018

0.021

0.41

0.46

0.54

C 0.008

0.010

0.014

0.20

0.254

0.35

D 0.547

0.550

0.553

13.89

13.97

14.05

E 0.447

0.450

0.453

11.35

11.43

11.51

e 0.044

0.050

0.056

1.12

1.27

1.42

0.490

0.510

0.530

12.45

12.95

13.46

0.390

0.410

0.430

9.91

10.41

10.92

0.585

0.590

0.595

14.86

14.99

15.11

0.485

0.490

0.495

12.32

12.45

12.57

L 0.075

0.090

0.095

1.91

2.29

2.41

- -

0.003

- -

0.075

- 10

Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions G

& G

are for PC Board surface mount pad pitch

design reference only.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions

unit: inches/mm

Detail "A"

Dimensions in inches

Dimensions in mm

Symbol

Min Nom

Max Min Nom

Max

A - -

0.047

- -

1.20

0.002

- 0.006

0.05 - 0.15

0.037

0.039

0.041

0.95

1.00

1.05

b 0.007

0.009

0.011

0.18

0.22

0.27

c 0.004

0.008

0.11 - 0.20

D 0.720

0.724

0.728

18.30

18.40

18.50

E -

0.315

0.319

8.00

8.10

0.020 BSC

0.50 BSC

0.779

0.787

0.795

19.80

20.00

20.20

L 0.016

0.020

0.024

0.40

0.50

0.60

- 0.032

- - 0.80 -

S - -

0.020

- -

0.50

y - -

0.003

- -

0.08

Notes:
1. The maximum value of dimension D

includes end flash.

2. Dimension E does not include resin fins.
3. Dimension S includes end flash.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Package Information

sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions

unit: inches/mm

Detail "A"

0.076MM

Detail "A"

SEATING PLANE

Dimensions in inches

Dimensions in mm

Symbol

Min Nom

Max Min Nom

Max

- -

0.049

- -

1.25

0.002

- -

0.05

- -

0.037

0.039

0.041

0.95

1.00

1.05

b 0.007

0.008

0.009

0.17

0.20

0.23

c 0.0056

0.0059

0.0062

0.142

0.150

0.158

E 0.311

0.315

0.319

7.90

8.00

8.10

0.020 TYP

0.50 TYP

D 0.520

0.528

0.535

13.20

13.40

13.60

0.461

0.465

0.469

11.70

11.80

11.90

L 0.012

0.020

0.028

0.30

0.50

0.70

0.0275

0.0315

0.0355

0.700

0.800

0.900

0.0109 TYP

0.278 TYP

Notes:
1. The maximum value of dimension D

includes end flash.

2. Dimension E does not include resin fins.
3. Dimension S includes end flash.

A29L004A Series

PRELIMINARY (March, 2005, Version 0.0)

AMIC Technology, Corp.

Package Information

sTSOP 32L TYPE I (8 X 14mm) Outline Dimensions

unit: inches/mm

Detail "A"

Pin1

Gage Plane

0.254

D y

Dimensions in inches

Dimensions in mm

Symbol

Min Nom

Max Min Nom

Max

- -

0.047

- -

1.20

0.002

- 0.006

0.05

- 0.15

0.037

0.039

0.041

0.95

1.00

1.05

b 0.0067

0.0087

0.0106

0.17

0.22

0.27

c 0.004

0.0083

0.10 - 0.21

E 0.311

0.315

0.319

7.90

8.00

8.10

- 0.0197

- - 0.50 -

D 0.543

0.551

0.559

13.80

14.00

14.20

0.484

0.488

0.492

12.30

12.40

12.50

L 0.020

0.024

0.028

0.50

0.60

0.70

y 0.000

- 0.003

0.00 - 0.076

Notes:
1. Dimension E does not include mold flash.
3. Dimension D

does not include interlead flash.

4. Dimension b does not include dambar protrusion.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A29L004AX

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A29L004AX