A42L2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Preliminary (November, 2001, Version 0.2)
AMIC Technology, Inc.
Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
June 13, 2001
Preliminary
0.1
Modify symbol H
E
dimensions in TSOP 24L package information
July 10, 2001
0.2
Add -45 grade and modify the AC, DC data
November 30, 2001
Add -U type spec.
A42L2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
PRELIMINARY (November, 2001, Version 0.2)
1
AMIC Technology, Inc.
Features
n
Organization: 4,194,304 words X 4 bits
n
Part Identification
- A42L2604
(2K Ref.)
- A42L2604-L
(2K Ref. with self-refresh)
n
Single 3.3V power supply/built-in VBB generator
n
Low power consumption
- Operating: 80mA (-45 max)
-
Standby: 1mA (TTL), 1mA (CMOS),
350
A (Self-refresh current)
n
High speed
- 45/50 ns RAS access time
- 20/22 ns column address access time
-
12/13 ns CAS access time
-
18/20 ns EDO Page Mode Cycle Time
n
Industrial operating temperature range: -40
C to +85
C
for -U
n
Fast Page Mode with Extended Data Out
n
2K Refresh Cycle in 32ms
n
Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n
TTL-compatible, three-state I/O
n
JEDEC standard packages
-
300mil, 24/26-pin SOJ
-
300mil, 24/26-pin TSOP type II package
General Description
The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and
Read operation via CAS pin.
The A42L2604 offers an accelerated Fast Page Mode
Pin Configuration
n
n
SOJ
n
n
TSOP
VCC
I/O
0
I/O
1
A3
CAS
I/O
2
I/O
3
VSS
A42L2604S
OE
WE
RAS
A10
A0
A1
A2
VCC
NC
VSS
A4
A5
A6
A7
A8
A9
13
12
11
10
9
8
6
5
4
3
2
1
14
15
16
17
18
19
21
22
23
24
25
26
VCC
I/O
0
I/O
1
A3
CAS
I/O
2
I/O
3
VSS
A42L2604V
OE
WE
RAS
A10
A0
A1
A2
VCC
NC
VSS
A4
A5
A6
A7
A8
A9
13
12
11
10
9
8
6
5
4
3
2
1
14
15
16
17
18
19
21
22
23
24
25
26
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.
Pin Descriptions
Symbol
Description
A0 A10
Address Inputs (2K product)
I/O
0
- I/O
3
Data Input/Output
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
VCC
3.3V Power Supply
VSS
Ground
NC
No Connection
A42L2604 Series
PRELIMINARY
(November, 2001, Version 0.2)
2
AMIC Technology, Inc.
Selection Guide
Symbol
Description
-45
-50
Unit
t
RAC
Maximum RAS Access Time
45
50
ns
t
AA
Maximum Column Address Access Time
20
22
ns
t
CAC
Maximum CAS Access Time
12
13
ns
t
OEA
Maximum Output Enable ( OE ) Access Time
12
13
ns
t
RC
Minimum Read or Write Cycle Time
76
84
ns
t
PC
Minimum EDO Cycle Time
18
20
ns
Functional Description
The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 4 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (t
cp
). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 s
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid V
IH
during Power-On to avoid current
surges.
A42L2604 Series
PRELIMINARY
(November, 2001, Version 0.2)
3
AMIC Technology, Inc.
Block Diagram
Recommended Operating Conditions
(Ta = 0
C to +70
C or -40
C to +85
C)
Symbol
Description
Min.
Typ.
Max.
Unit
VCC
Power Supply
3.0
3.3
3.6
V
VSS
Input High Voltage
0
0
0
V
V
IH
Input High Voltage
2.0
-
VCC + 0.3
V
V
IL
Input Low Voltage
-1.0
-
0.8
V
Control
Clocks
VBB Generator
Refresh Timer
Refresh control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Memory Array
4,194,304 X 4
Cells
Sense Amps & I/O
Data in
Buffer
Data out
Buffer
Vcc
Vss
RAS
CAS
WE
A0~A10
A0~A10
I/O
0
to
I/O
3
OE
A42L2604 Series
PRELIMINARY
(November, 2001, Version 0.2)
4
AMIC Technology, Inc.
Truth Table
Function
RAS
CAS
WE
OE
Address
I/Os
Standby
H
H
X
X
X
High-Z
Read: Word
L
L
H
L
Row/Col.
Data Out
Read
L
L
H
L
Row/Col.
Data Out
Write: Word (Early)
L
L
L
X
Row/Col.
Data In
Write (Early)
L
L
L
X
Row/Col.
Data In
Read-Write
L
L
H
L
L
H
Row/Col.
Data Out
Data In
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
L
L
H
L
H
L
H
H
H
L
H
L
Row/Col.
Col.
Data Out
Data Out
EDO-Page-Mode Write (Early)
-First cycle
-Subsequent Cycles
L
L
H
L
H
L
L
L
X
X
Row/Col.
Col.
Data In
Data In
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
L
L
H
L
H
L
H
L
H
L
L
H
L
H
Row/Col.
Col.
Data Out
Data In
Data Out
Data In
Hidden Refresh Read
L
H
L
L
H
L
Row/Col.
Data Out
Hidden Refresh Write
L
H
L
L
L
X
Row/Col.
Data In
High-Z
RAS -Only Refresh
L
H
X
X
Row
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
Self Refresh (L-ver only)
H
L
L
H
X
X
High-Z
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