A42U0616 Series

Preliminary

1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Features

Organization: 1,048,576 words X 16 bits

Part Identification

- A42U0616 (1K Ref.)

Single 2.5V power supply/built-in VBB generator

Low power consumption

- Operating: 120mA (-50 max)

Standby: 1mA (TTL), 0.2mA (CMOS),

250礎 (Self-refresh current)

High speed

- 50/60/80 ns RAS access time
- 25/30/40 ns column address access time

13/15/20 ns CAS access time

20/25/35 ns EDO Page Mode Cycle Time

Separate CAS (

UCAS

LCAS

) for byte selection

Fast Page Mode with Extended Data Out

Read-modify-write, RAS -only, CAS -before- RAS ,

Hidden refresh capability

TTL-compatible, three-state I/O

JEDEC standard packages

400mil, 42-pin SOJ

400mil, 50/44 TSOP type II package

General Description

The A42U0616 is a new generation randomly accessed
memory for graphics, organized in a 1,048,576 -word by
16-bit configuration. This product can execute Write and
Read operation via CAS pin.
The A42U0616 offers an accelerated Fast Page Mode

cycle with a feature called Extended Data Out (EDO).

Pin Configuration

SOJ

TSOP

VCC

I/O

A1
A2
A3

I/O

VSS

A42U0616S

RAS

I/O

VCC

UCAS

LCAS

I/O

VSS

16
17

13
14
15

VCC

I/O

A0
A1
A2

I/O

VSS

A42U0616V

RAS

I/O

VCC

VSS

LCAS
UCAS

I/O

VSS

17
18

14
15
16

VCC

VSS

VCC

This allow random access of up to 1024(1K Ref.) words
within a row at a 50/40/28 MHz EDO cycle, making the
A42U0616 ideally suited for graphics, digital signal
processing and high performance computing systems.

Pin Descriptions

Symbol

Description

A0 - A9

Address Inputs (1K product)

I/O

- I/O

Data Input/Output

RAS

Row Address Strobe

LCAS

Column Address Strobe for Lower Byte
(I/O

� I/O

)

UCAS

Column Address Strobe for Upper Byte
(I/O

� I/O

)

Write Enable

Output Enable

VCC

2.5V Power Supply

VSS

Ground

No Connection

A42U0616 Series

PRELIMINARY

(June, 2001, Version 0.0)

AMIC Technology, Inc.

Selection Guide

Symbol

Description

-50

-60

-80

Unit

RAC

Maximum RAS Access Time

Maximum Column Address Access Time

CAC

Maximum CAS Access Time

OEA

Maximum Output Enable ( OE ) Access Time

Minimum Read or Write Cycle Time

104

134

Minimum EDO Cycle Time

Functional Description

The A42U0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column address.

RAS and CAS are used to strobe the row address and the

column address, respectively.

The A42U0616 has two CAS inputs:

LCAS

controls I/O

I/O

, and

UCAS

controls I/O

I/O

UCAS

and

LCAS

function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS (

UCAS

LCAS

) to transition low and by the last to transition high.

Byte Read and Byte Write are controlled by using

LCAS

and

UCAS

separately.

A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or

CAS , whichever occurs later. The data inputs and outputs

are routed through 16 common I/O pins, with RAS , CAS ,

WE and OE controlling the in direction.

EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by

CAS . While holding RAS low, CAS can be toggled to

strobe changing column addresses, thus achieving shorter
cycle times.
The A42U0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which

keeps the output drivers on during the CAS precharge
time (t

). Since data can be output after CAS goes high,

the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.

A memory cycle is terminated by returning both RAS and

CAS high. Memory cell data will retain its correct state by

maintaining power and accessing all 1024(1K)
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.

Power-On

The initial application of the VCC supply requires a 200 祍
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid V

during Power-On to avoid current

surges.

A42U0616 Series

PRELIMINARY

(June, 2001, Version 0.0)

AMIC Technology, Inc.

Block Diagram

Recommended Operating Conditions

(Ta = 0

�

C to +70

�

Symbol

Description

Min.

Typ.

Max.

Unit

VCC

Power Supply

2.25

2.5

2.75

VSS

Input High Voltage

1.8

VCC + 0.2

Input Low Voltage

-1.0

0.8

Control

Clocks

VBB Generator

Refresh Timer

Refresh control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Memory Array

1,048,576 x 16

Cells

Sense Amps & I/O

Lower

Data in

Buffer

Lower

Data out

Buffer

Upper

Data in

Buffer

Upper

Data out

Buffer

Vcc
Vss

RAS

UCAS

LCAS

A0~A9

I/O

A42U0616 Series

PRELIMINARY

(June, 2001, Version 0.0)

AMIC Technology, Inc.

Truth Table

Function

RAS

UCAS

LCAS

Address

I/Os

Notes

Standby

High-Z

Read: Word

Row/Col.

Data Out

Read: Lower Byte

Row/Col.

I/O

0-7

= Data Out

I/O

8-15

= High-Z

Read: Upper Byte

Row/Col.

I/O

0-7

= High-Z

I/O

8-15

= Data Out

Write: Word

Row/Col.

Data In

Write: Lower Byte

Row/Col.

I/O

0-7

= Data In

I/O

8-15

= X

Write: Upper Byte

Row/Col.

I/O

0-7

= X

I/O

8-15

= Data In

Read-Write

Row/Col.

Data Out

Data In

1,2

EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles

L
L

H
H

Row/Col.

Col.

Data Out
Data Out

2
2

EDO-Page-Mode Write
-First cycle
-Subsequent Cycles

L
L

H
H

Row/Col.

Col.

Data In
Data In

1
1

EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles

L
L

Row/Col.

Col.

Data Out

Data In

Data Out

Data In

1, 2
1, 2

Hidden Refresh Read

Row/Col.

Data Out

Hidden Refresh Write

Row/Col.

Data In

High-Z

RAS -Only Refresh

Row

High-Z

CBR Refresh

High-Z

Self Refresh

High-Z

Note: 1. Byte Write may be executed with either

UCAS

LCAS

active.

2. Byte Read may be executed with either

UCAS

LCAS

active.

3. Only one

CAS

signal (

UCAS

LCAS

) must be active.

A42U0616 Series

PRELIMINARY

(June, 2001, Version 0.0)

AMIC Technology, Inc.

Absolute Maximum Ratings*

Input Voltage (Vin) . . . . . . . . . . . . . . . -0.5V to VCC+0.5V
Output Voltage (Vout) . . . . . . . . . . . . . -0.5V to VCC+0.5V
Power Supply Voltage (VCC) . . . . . . . -0.5V to VCC+0.5V
Operating Temperature (T

OPR

) . . . . . . . . . . 0

�

C to +70

�

Storage Temperature (T

STG

) . . . . . . . . . -55

�

C to +150

�

Soldering Temperature X Time (T

SOLDER

) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

�

C X 10sec

Power Dissipation (P

) . . . . . . . . . . . . . . . . . . . . . . . . 1W

Short Circuit Output Current (Iout) . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

DC Electrical Characteristics

(VCC = 2.5V

�

10%, VSS = 0V, Ta = 0

�

C to +70

�

-50

-60

-80

Symbol

Parameter

Min. Max. Min. Max. Min. Max.

Unit

Test Conditions

Notes

Input Leakage
Current

-5

�

Vin

Vin + 0.2V

Pins not under
Test = 0V

Output Leakage
Current

-5

�

OUT

disabled,

Vout

+ VCC

CC1

Operating Power
Supply Current

120

110

100

RAS

UCAS

LCAS

Address cycling; t

= min.

1, 2

CC2

TTL Standby Power
Supply Current

RAS

UCAS

LCAS

CC3

Average Power
Supply Current,

RAS Refresh Mode

120

110

100

RAS

cycling,

UCAS

LCAS

= V

= min.

CC4

EDO Page Mode
Average Power
Supply Current

100

RAS

UCAS

LCAS

Address

cycling; t

= min.

1, 2

CC5

CAS -before- RAS

Refresh Power
Supply Current

110

100

RAS

UCAS

LCAS

cycling; t

= min.

CC6

CMOS Standby
Power Supply
Current

0.2

RAS

UCAS

LCAS

VCC - 0.2V

CC7

Self Refresh Mode
Current

250

礎

RAS

CAS

VSS+0.2V

All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V

2.0

OUT

= -2mA

Output Voltage

0.4

OUT

= 2mA

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

AC Characteristics

(VCC = 2.5V

�

10%, VSS = 0V, Ta = 0

�

C to +70

�

Test Conditions:

Input timing reference level: V

=1.8V/0.8V

Output reference level: V

=1.6V/0.8V

Output Load: 1TTL gate + CL (100pF)
Assumed t

=2ns

-50

-60

-80

Std

Symbol

Parameter

Min.

Max. Min. Max. Min. Max.

Unit

Notes

Transition Time (Rise and Fall)

4, 5

REF

Refresh Period

Random Read or Write Cycle Time

104

134

RAS Precharge Time

RAS

RAS Pulse Width

10K

CAS

CAS Pulse Width

10K

RCD

RAS to CAS Delay Time

RAD

RAS to Column Address Delay Time

RSH

CAS to RAS Hold Time

CSH

CAS Hold Time

CRP

CAS to RAS Precharge Time

ASR

Row Address Setup Time

RAH

Row Address Hold Time

CLZ

CAS to Output in Low Z

RAC

Access Time from RAS

6,7

CAC

Access Time from CAS

6, 12

Access Time from Column Address

7, 12

Column Address Hold Time from RAS

RCS

Read Command Setup Time

RCH

Read Command Hold Time

RRH

Read Command Hold Time Reference
to RAS

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

AC Characteristics

(continued)

(VCC = 2.5V

�

10%, VSS = 0V, Ta = 0

�

C to +70

�

Test Conditions:

Input timing reference level: V

=1.8V/0.8V

Output reference level: V

=1.6V/0.8V

Output Load: 1TTL gate + CL (100pF)
Assumed t

=2ns

-50

-60

-80

Std

Symbol

Parameter

Min. Max. Min. Max. Min. Max.

Unit

Notes

RAL

Column Address to RAS Lead Time

COH

Output Hold After CAS Low

ODS

Output Disable Setup Time

OFF

Output Buffer Turn-Off Delay Time

8, 10

ASC

Column Address Setup Time

CAH

Column Address Hold Time

OES

Low to CAS High Set Up

WCS

Write Command Setup Time

WCH

Write Command Hold Time

WCR

Write Command Hold Time to RAS

Write Command Pulse Width

RWL

Write Command to RAS Lead Time

CWL

Write Command to CAS Lead Time

Data-in setup Time

Data-in Hold Time

DHR

Data-in Hold Time to RAS

RWC

Read-Modify-Write Cycle Time

110

135

180

RWD

RAS to WE Delay Time (Read-Modify-

Write)

107

CWD

CAS to WE Delay Time (Read-Modify-

Write)

AWD

Column Address to WE Delay Time
(Read-Modify-Write)

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

AC Characteristics (continued)

(VCC = 2.5V

�

10%, VSS = 0V, Ta = 0

�

C to +70

�

Test Conditions:

Input timing reference level: V

=1.8V/0.8V

Output reference level: V

=1.6V/0.8V

Output Load: 1TTL gate + CL (100pF)
Assumed t

=2ns

-50

-60

-80

Std

Symbol

Parameter

Min. Max. Min. Max. Min. Max.

Unit

Notes

OEH

OE Hold Time from WE

OEP

OE High Pulse Width

Read or Write Cycle Time (EDO Page)

CPA

Access Time from CAS Precharge
(EDO Page)

CAS Precharge Time (EDO Page)

PCM

EDO Page Mode RMW Cycle Time

CRW

EDO Page Mode CAS Pulse Width
(RMW)

RASP

RAS Pulse Width (EDO Page)

100K

CSR

CAS Setup Time ( CAS -before- RAS )

CHR

CAS Hold Time ( CAS -before- RAS )

RPC

RAS to CAS Precharge Time

( CAS -before- RAS )

ROH

RAS Hold Time Reference to OE

OEA

OE Access Time

OED

OE to Data Delay

OEZ

Output Buffer Turn-off Delay from OE

RASS

RAS pulse width (

-B-

self-refresh)

100

�

RPS

RAS precharge time

(

-B-

self-refresh)

104

134

CHS

CAS hold time (

-B-

self-refresh)

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Notes:
1. I

CC1

, I

CC3

, I

CC4

, and I

CC5

depend on cycle rate.

2. I

CC1

and I

CC4

depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200

�

s is required after power-up followed by any 8 RAS cycles before proper device operation is

achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of
8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.

4. AC Characteristics assume t

= 2ns. All AC parameters are measured with a load equivalent to one TTL load and

100pF, V

(min.)

GND and V

(max.)

VCC.

5. V

(min.) and V

(max.) are reference levels for measuring timing of input signals. Transition times are measured

between V

and V

6. Operation within the t

RCD

(max.) limit insures that t

RAC

(max.) can be met. t

RCD

(max.) is specified as a reference

point only. If t

RCD

is greater than the specified t

RCD

(max.) limit, then access time is controlled exclusively by t

CAC

7. Operation within the t

RAD

(max.) limit insures that t

RAC

(max.) can be met. t

RAD

(max.) is specified as a reference

point only. If t

RAD

is greater than the specified t

RAD

(max.) limit, then access time is controlled exclusively by t

8. Assumes three state test load (5pF and a 500

Thevenin equivalent).

9. Either t

RCH

or t

RRH

must be satisfied for a read cycle.

10. t

OFF

(max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. t

WCS

, t

WCH

, t

RWD

, t

CWD

and t

AWD

are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If t

WCS

(min.) and t

WCH

(min.), the cycle is an early write cycle

and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If t

RWD

(min.) , t

CWD

(min.) and t

AWD

(min.), the cycle is a read-modify-write cycle and the data out will contain data read from

the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is

indeterminate.

12. Access time is determined by the longer of t

or t

CAC

or t

CPA

13. t

ASC

to achieve t

(min.) and t

CPA

(max.) values.

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Word Read Cycle

RAS(3)

RP(2)

RC(1)

CRP(9)

CSH(8)

RCD(5)

RSH(7)

CAS(4)

ASR(10)

CRP(9)

RAH(11)

ASC(24)

CAH(25)

RAD(6)

RAL(20)

RCH(18)

RRH(19)

AR(16)

RCS(17)

ROH(51)

OEA(52)

RAC(13)

AA(15)

CAC(14)

CLZ(12)

OEZ(54)

OFF(23)

High-Z

: High or Low

Valid Data-out

Row Address

Column Address

I/O

Address

UCAS
LCAS

RAS

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Word Read-Modify-Write Cycle

RAS(3)

RP(2)

RWC(36)

CRP(9)

CSH(8)

RCD(5)

RSH(7)

CAS(4)

ASR(10)

CRP(9)

RAH(11)

CAH(25)

RAD(6)

Row Address

Column Address

Address

UCAS
LCAS

RAS

AR(16)

RWL(31)

ASC(24)

CWL(32)

AWD(39)

CWD38)

RWD(37)

WP(30)

OEA(52)

OEZ(54)

CLZ(12)

CAC(14)

OED(53)

AA(15)

RAC(13)

DS(33)

DH(34)

High-Z

Data-out

Data-in

: High or Low

I/O

OEH(40)

RCS(17)

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

EDO Page Mode Word Read Cycle

RASP(47)

RP(2)

RAS

UCAS

LCAS

CAS(4)

RCD(5)

CSH(8)

CRP(9)

PC(42)

RSH(7)

ASR(10)

RAH(11)

RAD(6)

AR(16)

RAL(20)

Address

I/O

: High or Low

ASC(24)

CP(44)

CSH(8)

ASC(24)

CAH(25)

Row

Column

RCH(25)

RCS(17)

RCH(25)

RCS(17)

CAH(25)

RRH(19)

OFF(23)

OEZ(54)

AA(15)

OEA(52)

OEP(41)

CAC(14)

CLZ(12)

OEZ(54)

CPA(43)

OES(26)

AA(15)

OEA(52)

COH(21)

CAC(14)

RAC(13)

CAC(14)

CLZ(12)

Data-out

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

EDO Page Mode Early Word Write Cycle

RASP(47)

RP(2)

RAS

UCAS

LCAS

CAS(4)

CP(44)

CAS(4)

CP(44)

CAS(4)

RCD(5)

CSH(8)

CRP(9)

PC(42)

RSH(7)

ASR(10)

RAH(11)

RAD(6)

ASC(24)

CAH(25)

ASC(24)

CAH(25)

ASC(24)

RAL(20)

Row

Column

Address

CWL(32)

WCH(28)

WCS(27)

Column

CWL(32)

WCH(28)

WCS(27)

WCH(28)

CWL(32)

RWL(31)

WP(30)

DH(34)

DS(33)

DH(34)

DS(33)

DH(34)

Data-in

I/O

: High or Low

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

EDO Page Mode Word Read-Modify-Write Cycle

RASP(47)

RAS

CAS(4)

CP(44)

CAS(4)

CP(44)

CAS(4)

RCD(5)

CSH(8)

CRP(9)

PCM(45)

RSH(7)

RP(2)

ASR(10)

RAH(11)

RAD(6)

ASC(24)

CAH(25)

ASC(24)

CAH(25)

ASC(24)

CAH(25)

RAL(20)

RCS(17)

CWD(38)

RWD(37)

CWL(32)

CWD(38)

CWL(32)

CWD(38)

CWL(32)

RWL(31)

OEA(52)

WP(30)

AWD(39)

ROH(51)

CAC(14)

AA(15)

RAC(13)

OED(53)

OEZ(54)

DS(33)

AA(15)

CPA(43)

DH(34)

OEZ(54)

OED(53)

DS(33)

DH(34)

OEZ(54)

DS(33)

OED(53)

DH(34)

AA(15)

CPA(43)

CLZ(12)

High-Z

: High or Low

I/O

Address

UCAS
LCAS

Data-out

Data-in

Data-out

Data-in

Data-out

Data-in

Row

Column

OEH(40)

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)

RAS

: High or Low

I/O

Address

UCAS

RP(2)

RASP(47)

CRP(9)

CSH(8)

RCD(5)

CAS(4)

CP(44)

CAS(4)

CP(44)

CAS(4)

CPR(9)

RSH(7)

PC(42)

Row

Column

RAL(20)

CAH(25)

ASC(24)

CAH(25)

ASC(24)

CAH(25)

ASC(24)

ASR(10)

RAH(11)

RAD(6)

Column

RCS(17)

RCH(18)

WCS(27)

WCH(28)

Data-out

Data-in

DH(34)

DS(33)

AA(15)

CAP(43)

CAC(14)

COH(21)

AA(15)

RAC(13)

CAC(14)

OEA(52)

LCAS

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Self Refresh Mode

Self Refresh Mode.

a. Entering the Self Refresh Mode:

The A42U0616 Self Refresh Mode is entered by using

CAS

before

RAS

cycle and holding

RAS

and

CAS

signal

"low" longer than 100

�

b. Continuing the Self Refresh Mode:

The Self Refresh Mode is continued by holding

RAS

"low" after entering the Self Refresh Mode.

It does not depend on

CAS

being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode.

c. Exiting the Self Refresh Mode:

The A42U0616 exits the Self Refresh Mode when the

RAS

signal is brought "high".

RASS(55)

RP(2)

CRP(9)

CSR(48)

RPC(50)

RAS

RPS(56)

CHS(57)

ASR(10)

CPN(42)

OFF(23)

A0 ~ A7

: High or Low

High-Z

I/O

UCAS
LCAS

ROW

COL

Note: WE, OE = Don't care.

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Capacitance

(Ta = Room Temperature, VCC = 2.5V

�

10%)

Symbol

Signals

Parameter

Max.

Unit

Test Conditions

IN1

A0 � A9

Vin = 0V

IN2

RAS

CAS

Input Capacitance

Vin = 0V

I/O

- I/O

I/O Capacitance

Vin = Vout = 0V

Ordering Codes

Package\ RAS Access Time

50ns

60ns

80ns

Refresh

Cycle

Self-

Refresh

42L SOJ (400mil)

A42U0616S-50

A42U0616S-60

A42U0616S-80

Yes

50(44)L TSOP type II (400mil)

A42U0616V-50

A42U0616V-60

A42U0616V-80

Yes

A42U0616 Series

PRELIMINARY (June, 2001, Version 0.0)

AMIC Technology, Inc.

Package Information

SOJ 42L Outline Dimensions

unit: inches/mm

Dimensions in inches

Dimensions in mm

Symbol

Min

Nom

Max

Min

Nom

Max

0.128

0.138

0.148

3.25

3.51

3.76

0.025

0.64

0.105

0.110

0.115

2.67

2.79

2.92

0.026

0.028

0.032

0.66

0.71

0.81

0.015

0.018

0.020

0.38

0.46

0.51

0.007

0.008

0.013

0.18

0.20

0.33

1.075

1.080

1.085

27.31

27.43

27.56

0.395

0.400

0.405

10.03

10.16

10.29

0.050

1.27

0.370

9.4

0.435

0.440

0.445

11.05

11.18

11.30

0.082

2.08

0.045

1.14

0.003

0.075

�

Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e

is for PC Board surface mount pad pitch design

reference only.
4. Dimension S includes end flash.

Seating Plane

D y

A42U0616 Series

PRELIMINARY

(June, 2001, Version 0.0)

AMIC Technology, Inc.

Package Information

TSOP 50/44L (Type II) Outline Dimensions

unit: inches/mm

D y

Detail "A"

Seating Plane

RAD R1

RAD R

Dimensions in inches

Dimensions in mm

Symbol

Min

Nom

Max

Min

Nom

Max

0.048

1.20

0.002

0.006

0.05

0.15

0.037

0.039

0.042

0.95

1.00

1.05

0.012

0.018

0.30

0.45

0.005

0.008

0.12

0.21

0.820

0.825

0.830

20.82

20.95

21.08

0.400 BSC

10.16 BSC

0.463 BSC

11.76 BSC

0.016

0.020

0.024

0.40

0.50

0.60

0.031 REF

0.80 REF

0.031 BSC

0.80 BSC

0.005

0.010

0.12

0.25

0.005

0.12

0.0435 REF

0.875 BSC

0�

5�

0�

5�

Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: A42U0616S-50

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: A42U0616S-50