A43L0616A
512K X 16 Bit X 2 Banks Synchronous DRAM
(May, 2001, Version 1.0)
AMIC Technology, Inc.
Document Title
512K X 16 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
December 4, 2000
Preliminary
0.1
Add input/output capacitance specification
February 13, 2001
Add Cl2 spec for (-5, -5.5, -6)
Modify MRS Set Cycle Waveform error
0.2
Add -U for industrial operating temperature range
April 11, 2001
1.0
Final spec. release
May 29, 2001
Final
Some AC parameter unit update
A43L0616A
512K X 16 Bit X 2 Banks Synchronous DRAM
(May, 2001, Version 1.0)
1
AMIC Technology, Inc.
Features
n
JEDEC standard 3.3V power supply
n
LVTTL compatible with multiplexed address
n
Dual banks / Pulse RAS
n
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
n
All inputs are sampled at the positive going edge of the
system clock
n
Industrial operating temperature range: -40C to +85C
for -U
n
Burst Read Single-bit Write operation
n
DQM for masking
n
Auto & self refresh
n
32ms refresh period (2K cycle)
n
50 Pin TSOP (II)
General Description
The A43L0616A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 524,288 words by 16
bits, fabricated with AMIC's high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
n
n
TSOP (II)
A43L0616AV
50 49 48 47 46 45 44 43 42 41
39
40
38 37 36 35 34 33 32 31 30 29 28 27 26
1
2
3
4 5
6
7
8
9 10
12
11
13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
DQ
15
DQ
14
VSSQ
DQ
13
DQ
12
VDDQ
DQ
11
DQ
10
VSSQ
DQ
9
DQ
8
VDDQ
NC/RFU
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ
0
DQ
1
VSSQ
DQ
2
DQ
3
VDDQ
DQ
4
DQ
5
VSSQ
DQ
6
DQ
7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
A43L0616A
(May, 2001, Version 1.0)
2
AMIC Technology, Inc.
Block Diagram
Bank Select
Row Buffer
Refresh Counter
Address Register
Row Decoder
Column Buffer
LCBR
LRAS
CLK
ADD
Timing Register
Data Input Register
512K X 16
512K X 16
Sense AMP
Column Decoder
Latency & Burst Length
Programming Register
LRAS
LCAS
LRAS
LCBR
LWE
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
I/O Control
Output Buffer
LWE
LDQM
DQi
A43L0616A
(May, 2001, Version 1.0)
3
AMIC Technology, Inc.
Pin Descriptions
Symbol
Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
A0~A10/AP
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power
Supply/Ground
Power Supply: +3.3V
0.3V/Ground
VDDQ/VSSQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU
No Connection
A43L0616A
(May, 2001, Version 1.0)
4
AMIC Technology, Inc.
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
C to +150
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if "Absolute
Maximum Ratings" are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.
Capacitance (T
A
=25
C, f=1MHz)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Capacitance
CI1
A0 to A10, BA
2
4
pF
CI2
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
UDQM, LDQM
2
4
pF
Data Input/Output Capacitance
CI/O
DQ0 to DQ15
2
6
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, T
A
= 0C to +70C or -40C to +85C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VDD,VDDQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
3.0
VDD+0.3
V
Input Low Voltage
V
IL
-0.3
0
0.8
V
Note 1
Output High Voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output Low Voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input Leakage Current
I
IL
-5
-
5
A
Note 2
Output Leakage Current
I
OL
-5
-
5
A
Note 3
Output Loading Condition
See Figure 1
Note: 1. V
IL
(min) = -1.5V AC (pulse width
5ns).
2. Any input 0V
VIN
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
Vout
VDD
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