LP62E16512-T Series

512K X 16 BIT LOW VOLTAGE CMOS SRAM

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Features

Operating voltage: 1.65V to 2.2V
Access times: 70 ns (max.)
Current:

Very low power version: Operating: 40mA (max.)

Standby: 10

A (max.)

Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 1.2V (min.)
Available in 48-ball CSP (8

10mm) packages

General Description

The LP62E16512-T is a low operating current 8,388,608-bit
static random access memory organized as 524,288 words
by 16 bits and operates on low power voltage from 1.65V to
2.2V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 1.2V.

Product Family

Power Dissipation

Product

Family

Operating

Temperature

VCC Range

Speed

Data

Retention

CCDR

, Typ.)

Standby

SB1

, Typ.)

Operating

CC2

, Typ.)

Package

Type

LP62E16512

-25

C ~ +85

1.65V~2.2V 70ns

0.1

A 0.5

3mA 48

CSP

1. Typical values are measured at VCC = 1.8V, T

= 25

C and not 100% tested.

2. Data retention current VCC = 1.2V.

Pin Configurations

CSP (Chip Size Package)

48-pin Top View

I/O

GND

VCC

I/O

A18

A12

A10

A11

A13

A14

A15

I/O

GND

VCC

I/O

A17

A16

I/O

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Pin Description - CSP

Symbol Description Symbol Description

A0 - A18

Address Inputs

Higher Byte Enable Input
(I/O

- I/O

)

CS , CS

Chip Enable

Output Enable

I/O

- I/O

Data Input/Output

VCC

Power Supply

Write Enable Input

GND

Ground

Byte Enable Input
(I/O

- I/O

)

NC No

Connection

Recommended DC Operating Conditions

= -25

C to + 85

Symbol Parameter Min.

Typ.

Max. Unit

VCC Supply

Voltage

1.65

1.8

2.2

GND

Ground

0 0 0

Input High Voltage

1.4

VCC + 0.3

Input Low Voltage

-0.3

+0.4

Output

Load

TTL Output

Load

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Absolute Maximum Ratings*

VCC to GND .............................................. -0.5V to +3.0V
IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...................-25

C to +85

Storage Temperature, Tstg.....................-55

C to +125

Power Dissipation, P

T.......................................................................

0.7W

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect
device reliability.

DC Electrical Characteristics

= -25

C to + 85

C, VCC = 1.65V to 2.2V, GND = 0V)

Symbol Parameter

LP62E16512-70LLT

Unit

Conditions

Min.

Max.

Input Leakage Current

= GND to VCC

Output Leakage Current

CS = V

or CS

= V

LB = HB = V

I/O

= GND to VCC

Active Power Supply
Current

- 5

CS = V

, CS

= V

LB = V

or HB = V

IL ,

I/O

= 0mA

CC1

Dynamic Operating

- 40

Min. Cycle, Duty = 100%,

CS = V

= V

, LB = V

or HB = V

I/O

= 0mA

CC2

Current

- 5

0.2V, CS

VCC-0.2V ,

0.2V or HB

0.2V

f = 1MHz , I

I/O

= 0mA

CS = V

= V

LB = HB = V

SB1

Standby Current

- 10

VCC - 0.2V or CS

0.2V or

LB = HB

VCC-0.2V

VCC-0.2V or V

0.2V

Output Low Voltage

0.2

= 0.1 mA

Output High Voltage

1.4

= -1.0 mA

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Truth Table

I/O

to I/O

Mode

I/O

to I/O

Mode

VCC Current

High - Z

SB1

, I

High - Z

SB1

, I

High - Z

SB1

, I

L L

Read

CC1

, I

CC2

, I

L H L H L H Read

High

CC1

, I

CC2

, I

High

Read

CC1

, I

CC2

, I

L L

Write

CC1

, I

CC2

, I

L H X L L H Write

High

CC1

, I

CC2

, I

High

Write

CC1

, I

CC2

, I

High - Z

CC1

, I

CC2

, I

High - Z

CC1

, I

CC2

, I

Note: X = H or L

Capacitance

= 25

C, f = 1.0MHz)

Symbol Parameter Min.

Max.

Unit

Conditions

* Input

Capacitance

6 pF V

= 0V

I/O

* Input/Output

Capacitance 8 pF V

I/O

= 0V

* These parameters are sampled and not 100% tested.

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

AC Characteristics

= -25

C to +85

C, VCC = 1.65V to 2.2V)

Symbol Parameter

LP62E16512-70LLT

Unit

Min.

Max.

Read Cycle

Read Cycle Time

Address Access Time

Acs1 ,

Acs2

Chip Enable Access Time

Byte Enable Access Time

Output Enable to Output Valid

CLZ1 ,

CLZ2

Chip Enable to Output in Low Z

BLZ

Byte Enable to Output in Low Z

OLZ

Output Enable to Output in Low Z

CHZ1 ,

CHZ2

Chip Disable to Output in High Z

BHZ

Byte Disable to Output in High Z

OHZ

Output Disable to Output in High Z

Output Hold from Address Change

Write Cycle

Write Cycle Time

CW1 ,

CW2

Chip Enable to End of Write

Byte Enable to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

WHZ

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

Note: t

CLZ1 ,

CLZ2 ,

BLZ

, t

OLZ

, t

CHZ1

, t

CHZ2 ,

BHZ

and t

OHZ

and t

WHZ

are defined as the time at which the outputs achieve the open

circuit condition and are not referred to output voltage levels.

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Timing Waveforms

Read Cycle 1

(1, 2, 4)

Address

OUT

Read Cycle 2

(1, 2, 3)

Address

ACS1 ,

ACS2

CHZ1

CHZ2

HB, LB

BHZ5

BLZ5

OLZ5

OHZ5

OUT

CLZ1 ,

CLZ2

Notes: 1.

is high for Read Cycle.

2. Device is continuously enabled

CS = V

, or CS

= V

, HB = V

and, or LB = V

3. Address valid prior to or coincident with

CS and ( HB and, or LB ) transition low or CS

transition High.

= V

5. Transition is measured

200mV from steady state. This parameter is sampled and not 100% tested.

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Timing Waveforms (continued)

Write Cycle 3
(Byte Enable Controlled)

Address

WR3

CW1 ,

CW2

BW2

AS1

DATA IN

DATA OUT

HB, LB

WHZ4

Notes: 1. t

is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (t

, t

) of a low

CS , WE and ( HB and , or LB ) or a high CS

is measured from the earliest of

CS or WE or ( HB and , or LB ) going high or CS

going Low to the end of the

Write cycle.

OE level is high or low.

5. Transition is measured

200mV from steady state. This parameter is sampled and not 100% tested.

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

AC Test Conditions

Input Pulse Levels

0.2V to VCC-0.2V

Input Rise And Fall Time

5 ns

Input and Output Timing Reference Levels

0.8V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

TTL

5pF

TTL

Figure 1. Output Load

Figure 2. Output Load for t

CLZ1

, t

CLZ2

, t

BHZ

, t

BLZ

OLZ

, t

CHZ1

, t

CHZ2 ,

OHZ

, t

WHZ

, and t

Data Retention Characteristics

= -25

C to 85

Symbol Parameter Min.

Max.

Unit

Conditions

VCC for Data Retention

1.2

2.2

VCC - 0.2V or

0.2V or

LB = HB

VCC-0.2V

CCDR

Data Retention Current

- 0.2*

VCC = 1.2V,

VCC - 0.2V or

0.2V or

LB = HB

VCC-0.2V

VCC-0.2V or V

0.2V

CDR

Chip Disable to Data Retention Time

Operation Recovery Time

- ns

See Retention Waveform

VCC Rising Time from Data Retention
Voltage to Operating Voltage

5 -

* LP62E16512 - 70LLT

CCDR

: max. 0.1

A at T

= 25

(0.2

A at T

= 0

C to + 40

C )

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Low VCC Data Retention Waveform (1) (

CS1

Controlled)

VCC

CS1

CDR

1.65V

DATA RETENTION MODE

1.2V

CS1

- 0.2V

Low VCC Data Retention Waveform (2) (CS2 Controlled)

VCC

CS2

CDR

1.65V

DATA RETENTION MODE

1.2V

0.2V

CS2

Ordering Information

Part No.

Access Time(ns)

Operating Current

Max.(mA)

Standby Current

Max.(uA)

Package

LP62E16512U-70LLT 40

48L

CSP

LP62E16512U-70LLTF

48L Pb-Free CSP

LP62E16512-T Series

(August, 2004, Version 1.1)

AMIC Technology, Corp.

Package Information

48LD CSP ( 8 x 10 mm ) Outline Dimensions

unit: mm

(48TFBGA)

A
B
C
D
E
F

G
H

TOP VIEW

Ball#A1 CORNER

SIDE VIEW

SEATING PLANE

A
B
C
D
E
F

G
H

1 2 3 4 5 6

0.10

0.25

A B

b (48X)

BOTTOM VIEW

Ball*A1 CORNER

0.20(4X)

0.10

Dimensions in mm

Symbol

MIN.

NOM.

MAX.

A ---

---

1.20

0.20

0.25

0.30

0.48

0.53

0.58

D 7.90

8.00

8.10

E 9.90

10.00

10.10

---

3.75

---

5.25

---

e ---

0.75

---

b 0.30

0.35

0.40

Notes:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS

ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS

OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE

SOLDER BALL AND THE BODY EDGE.

5. BALL PAD OPENING OF SUBSTRATE IS

0.3mm (SMD)

SUGGEST TO DESIGN THE PCB LAND SIZE AS

0.3mm (NSMD)

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