A615308 Series
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
PRELIMINARY
(January, 2001, Version 0.0)
AMIC Technology, Inc.
Document Title
32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
January 17, 2001
A615308 Series
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
PRELIMINARY
(January, 2001, Version 0.0)
1
AMIC Technology, Inc.
Features
n
Single +5V power supply
n
Access times: 12 ns (max.)
n
Current: Operating: 150mA (max.)
Standby: 12mA (max.)
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL compatible
n
Common I/O using three-state output
n
Data retention voltage: 2V (min.)
n
Available in 28-pin SOJ and TSOP packages
General Description
The A615308 is a high-speed 262,144-bit static random
access memory organized as 32,768 words by 8 bits and
operates on a single 5V power supply. It is built using
high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
CE
is at a high level, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n
SOJ
n
n
TSOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
OE
A11
A9
A8
A13
WE
VCC
A10
A615308S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A615308V
1
9
28
20
A11
2
3
4
5
6
7
8
10
11
12
13
14
A9
A8
A13
A14
A12
A7
A6
A5
A4
A3
27
26
25
24
23
22
21
19
18
17
16
15
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A0
A1
A2
A10
VCC
I/O
7
OE
WE
CE
~~
~~
A615308 Series
PRELIMINARY
(January, 2001, Version 0.0)
2
AMIC Technology, Inc.
Block Diagram
ROW
DECODER
512 X 512
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
CE
WE
I/O
7
I/O
0
A14
A13
A12
A0
VCC
GND
OE
Pin Description - SOJ
Pin No.
Symbol
Description
1 - 10, 21,
23 - 26
A0 - A14
Address Inputs
11 - 13, 15 - 19
I/O
0
- I/O
7
Data Inputs/Outputs
20
CE
Chip Enable
22
OE
Output Enable
27
WE
Write Enable
28
VCC
Power Supply
14
GND
Ground
Pin Description - TSOP
Pin No.
Symbol
Description
2 - 5, 8 - 17, 28
A0 - A14
Address Inputs
18 - 20, 22 - 26
I/O
0
- I/O
7
Data Inputs/Outputs
27
CE
Chip Enable
1
OE
Output Enable
6
WE
Write Enable
7
VCC
Power Supply
21
GND
Ground
A615308 Series
PRELIMINARY
(January, 2001, Version 0.0)
3
AMIC Technology, Inc.
Recommended DC Operating Conditions
(T
A
= 0
C to + 70
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
3.5
VCC + 0.5
V
V
IL
Input Low (1) Voltage
-0.5
0
+0.8
V
C
L
Output Load
-
-
30
pF
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0
C to +70
C
Storage Temperature, Tstg . . . . . . . . . . -55
C to +125
C
Temperature Under Bias, Tbias . . . . . . . . -10
C to +85
C
Power Dissipation, P
T
. . . . . . . . . . . . . . . . . . . . . . . 1.0W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
(T
A
= 0
C to + 70
C, VCC = 5V
10%, GND = 0V)
Symbol
Parameter
A615308-12
Unit
Conditions
Min.
Max.
I
LI
Input Leakage
-
2
A
V
IN
= GND to VCC
I
LO
Output Leakage
-
2
A
CE
= V
IH
or OE = V
IH
V
I/O
= GND to VCC
I
CC1
(2)
Dynamic Operating
Current
-
150
mA
CE
= V
IL
, I
I/O
= 0 mA
Min. Cycle, Duty = 100%
I
SB
-
35
mA
CE
= V
IH
I
SB1
Standby Power
Supply Current
-
12
mA
CE
VCC - 0.2V
V
IN
VCC -0.2V or
V
IN
0.2V
V
OL
Output Low Voltage
-
0.4
V
I
OL
= 8 mA
V
OH
Output High Voltage
2.4
-
V
I
OH
= -4 mA
Notes: 1. V
IL
= -3.0V for pulses less than 20 ns.
2. I
CC1
is dependent on output loading, cycle rates, and Read/Write patterns.
A615308 Series
PRELIMINARY
(January, 2001, Version 0.0)
4
AMIC Technology, Inc.
Truth Table
Mode
CE
OE
WE
I/O Operation
Supply Current
Standby
H
X
X
High Z
I
SB
, I
SB1
Output Disable
L
H
H
High Z
I
CC1
Read
L
L
H
D
OUT
I
CC1
Write
L
X
L
D
IN
I
CC1
Note: X = H or L
Capacitance
(T
A
= 25
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
-
10
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
-
10
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0
C to +70
C, VCC = 5V
10%)
Symbol
Parameter
A615308-12
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
12
-
ns
t
AA
Address Access Time
-
12
ns
t
ACE
Chip Enable Access Time
-
12
ns
t
OE
Output Enable to Output Valid
-
6
ns
t
CLZ
Chip Enable to Output in Low Z
3
-
ns
t
OLZ
Output Enable to Output in Low Z
0
-
ns
t
CHZ
Chip Disable Output in High Z
0
6
ns
t
OHZ
Output Disable to Output in High Z
0
6
ns
t
OH
Output Hold from Address Change
3
-
ns
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