A617308.PDF
A617308 Series
Preliminary
128K X 8 BIT HIGH SPEED CMOS SRAM
PRELIMINARY
(January, 2000, Version 0.2)
AMIC Technology, Inc.
Document Title
128K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
September 17, 1999
Preliminary
0.1
Change V
DR
(Max.) from 3.6V to 5.5V
November 30, 1999
Add 32-pin SOP package
Modify 32-pin SOJ package outline drawing and
Dimensions
0.2
Add 15ns part
January 19, 2000
Change operating current from 180mA to 150mA (Max.)
Change V
DR
(Min.) from 2V to 3V
Remove 32-pin SOP package
A617308 Series
Preliminary
128K X 8 BIT HIGH SPEED CMOS SRAM
PRELIMINARY
(January, 2000, Version 0.2)
1
AMIC Technology, Inc.
Features
n
Single + 5V power supply
n
Access times: 10/12/15 ns (max.)
n
Current: Operating: 150mA (max.)
Standby:
12mA (max.)
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL compatible
n
Common I/O using three-state output
n
Data retention voltage: 3V (min.)
n
Available in 32-pin SOJ and TSOP packages
General Description
The A617308 is a high-speed, low-power 1,048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply. It is built using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Minimum standby power is drawn by this device when
chip enable is disable, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 3V.
Pin Configurations
n
SOJ
n
n
TSOP
A10
7
6
5
4
3
GND
OE
CE1
2
1
0
1
9
32
24
A11
A9
2
3
4
5
6
7
8
10
11
12
13
14
15
16
A8
A13
VCC
NC
A14
A12
A7
A6
A5
A4
31
30
29
28
27
26
25
23
22
21
20
19
18
17
I/O
I/O
I/O
I/O
I/O
A0
A1
A2
A3
A15
WE
CE2
I/O
I/O
I/O
~~
~~
A16
A617308V
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
I/O
1
I/O
2
I/O
3
GND
I/O
4
I/O
5
I/O
6
I/O
7
A10
A9
A8
A13
CE2
A15
VCC
A11
A617308S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
CE1
WE
A16
A617308 Series
PRELIMINARY
(January, 2000, Version 0.2)
2
AMIC Technology, Inc.
Block Diagram
Pin Descriptions SOJ
Pin No.
Symbol
Description
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
13 - 15,
17 - 21
I/O
0
- I/O
7
Data Inputs/Outputs
22
CE1
Chip Enable 1
30
CE2
Chip Enable 2
24
OE
Output Enable
29
WE
Write Enable
32
VCC
Power Supply
16
GND
Ground
1
NC
No Connection
Pin Description - TSOP
Pin No.
Symbol
Description
1 - 4, 7,
10 - 20, 31
A0 - A16
Address Inputs
21 - 23,
25 - 29
I/O
0
- I/O
7
Data Inputs/Outputs
30
CE1
Chip Enable 1
6
CE2
Chip Enable 2
32
OE
Output Enable
5
WE
Write Enable
8
VCC
Power Supply
24
GND
Ground
9
NC
No Connection
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
CONTROL
LOGIC
CE1
A16
A0
OE
WE
8
8
8
I/O
0
- I/O
7
CE2
A617308 Series
PRELIMINARY
(January, 2000, Version 0.2)
3
AMIC Technology, Inc.
Recommended DC Operating Conditions
(T
A
= 0
C to + 70
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
VCC + 0.5
V
V
IL
Input Low (1) Voltage
-0.5
0
+0.8
V
C
L
Output Load
-
-
30
pF
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . . 0
C to +70
C
Storage Temperature, Tstg . . . . . . . . . . -55
C to +125
C
Temperature Under Bias, Tbias . . . . . . . . -10
C to +85
C
Power Dissipation, P
T
. . . . . . . . . . . . . . . . . . . . . . . 1.0W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
(T
A
= 0
C to + 70
C, VCC = 5V
10%, GND = 0V)
Symbol
Parameter
A617308-10/12/15
Unit
Conditions
Min.
Max.
I
LI
Input Leakage
-
5
A
V
IN
= GND to VCC
I
LO
Output Leakage
-
5
A
1
CE = V
IH
, CE2= V
IL
or OE = V
IH
V
I/O
= GND to VCC
I
CC1
(2)
Dynamic Operating Current
-
150
mA
1
CE = V
IL
, CE2 = V
IH
, I
I/O
= 0 mA
Min. Cycle, Duty = 100%
I
SB
-
35
mA
1
CE = V
IH
or CE2 = V
IL
I
SB1
Standby Power
Supply Current
-
12
mA
1
CE
VCC - 0.2V, CE2
0.2V
V
IN
VCC -0.2V or V
IN
0.2V
V
OL
Output Low Voltage
-
0.4
V
I
OL
= 8 mA
V
OH
Output High Voltage
2.4
-
V
I
OH
= -4 mA
Notes: 1. V
IL
= -3.0V for pulses less than 20 ns.
2. I
CC1
is dependent on output loading, cycle rates, and Read/Write patterns.
A617308 Series
PRELIMINARY
(January, 2000, Version 0.2)
4
AMIC Technology, Inc.
Truth Table
Mode
1
CE
CE2
OE
WE
I/O Operation
Supply Current
H
X
X
X
High Z
I
SB
, I
SB1
Standby
X
L
X
X
High Z
I
SB
, I
SB1
Output Disable
L
H
H
H
High Z
I
CC1
Read
L
H
L
H
D
OUT
I
CC1
Write
L
H
X
L
D
IN
I
CC1
Note: X = H or L
Capacitance
(T
A
= 25
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
-
8
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
-
8
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0
C to +70
C, VCC = 5V
10%)
Symbol
Parameter
A617308-10
A617308-12
A617308-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
10
-
12
-
15
-
ns
t
AA
Address Access Time
-
10
-
12
-
15
ns
t
ACE
Chip Enable Access Time
-
10
-
12
-
15
ns
t
OE
Output Enable to Output Valid
-
5
-
6
-
8
ns
t
CLZ
Chip Enable to Output in Low Z
3
-
3
-
3
-
ns
t
OLZ
Output Enable to Output in Low Z
0
-
0
-
0
-
ns
t
CHZ
Chip Disable Output in High Z
0
5
0
6
-
8
ns
t
OHZ
Output Disable to Output in High Z
0
5
0
6
0
8
ns
t
OH
Output Hold from Address Change
3
-
3
-
3
-
ns
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