A63G7332 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary
with Burst Counter and Pipelined Data Output
PRELIMINARY (December, 1998, Version 2.1)
AMIC Technology, Inc.
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No.
History
Issue Date
Remark
1.0
Initial issue
November, 1997
Preliminary
1.1
Change pin 14 description from VCC to NC
June 17, 1998
Change package type from 100-pin TQFP to 100-pin LQFP
2.0
Change fast access times from 4.5/5/5.5 ns to 4.2/4.5/5.0 ns
August 27, 1998
2.1
Modify 100-pin LQFP symbol y dimensions -
December 31, 1998
Max. in mm : 0.08
0.1
Max. in inches : 0.003
0.004
A63G7332 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary
with Burst Counter and Pipelined Data Output
PRELIMINARY (December, 1998, Version 2.1)
1
AMIC Technology, Inc.
Features
n
Fast access times: 4.2/4.5/5.0 ns (143/133/100 MH
Z
)
n
Single +3.3V+10% or +3.3V-5% power supply
n
Separate +2.5V+0.4V/-0.12V isolated output buffer
n
3.3V tolerant inputs
n
Synchronous burst function
n
Individual Byte Write control and Global Write
n
Registered output for pipelined applications
n
Three separate chip enables allow wide range of
options for CE control, address pipelining
n
Selectable BURST mode
n
SLEEP mode (ZZ pin) provided
n
Available in 100-pin LQFP package
General Description
The A63G7332 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63G7332 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 128K X 32 SRAM core to provide
a wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A16), all data inputs (I/O
1
- I/O
32
), active LOW chip
enable ( CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1, BW2 , BW3 , BW4 ) and Global
Write ( GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63G7332
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O
1
- I/O
8
, BW2 controls I/O
9
- I/O
16
, BW3
controls I/O
17
- I/O
24
, and BW4 controls I/O
25
- I/O
32
, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1)
4
AMIC Technology, Inc.
Pin Description
Pin No.
Symbol
Description
32 - 37, 44 - 50, 81,
82, 99, 100
A0 - A16
Address Inputs
89
CLK
Clock
87, 93 - 96
BWE
, BW1 - BW4
Byte Write Enables
88
GW
Global Write
86
OE
Output Enable
92, 97, 98
CE2
,CE2, CE
Chip Enables
83
ADV
Burst Address Advance
84
ADSP
Processor Address Status
85
ADSC
Controller Address Status
31
MODE
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64
ZZ
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
2, 3, 6 - 9, 12, 13,
18, 19, 22 - 25, 28,
29, 52, 53, 56 - 59,
62, 63, 68, 69,
72 - 75, 78, 79
I/O
1
- I/O
32
Data Inputs/Outputs
1,14,16, 30, 38, 39,
42, 43, 51, 66, 80
NC
No Connection
14, 15, 41, 65, 91
VCC
Power Supply
17, 40, 67, 90
GND
Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ
Isolated Output Buffer Ground
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