A63L73321
128K X 32 Bit Synchronous High Speed SRAM
Preliminary
with Burst Counter and Flow-through Data Output
PRELIMINARY (August, 2000, Version 0.4)
AMIC Technology, Inc.
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-
through Data Output
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
December 14, 1998
Preliminary
0.1
Change fast access times from 8.5/9.5/10 ns to 9.5/10/12 ns June 9, 1999
Change I
CC1
from 300mA to 350mA(max.)
0.2
Add description for 100/91/83 MHz
December 19, 1999
0.3
Add description for 2E1D at page 1
June 20, 2000
Modify waveform at page 11
0.4
Delete -9.5 & -10 part number
August 29, 2001
Change -12 cycle time from 12ns to 15ns
A63L73321
128K X 32 Bit Synchronous High Speed SRAM
Preliminary
with Burst Counter and Flow-through Data Output
PRELIMINARY (August, 2000, Version 0.4)
1
AMIC Technology, Inc.
Features
n
Fast access times: 12ns at 66MHz
n
Single +3.3V+10% or +3.3V-5% power supply
n
Synchronous burst function
n
Individual Byte Write control and Global Write
n
Double-cycle enable, single-cycle deselect
n
Three separate chip enables allow wide range of
options for CE control, address pipelining
n
Selectable BURST mode
n
SLEEP mode (ZZ pin) provided
n
Available in 100-pin LQFP package
General Description
The A63L73321 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63L73321 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 128K X 32 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A16), all data inputs (I/O
1
- I/O
32
), active LOW chip enable
( CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global
Write ( GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L73321
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O
1
- I/O
8
, BW2 controls I/O
9
- I/O
16
, BW3
controls I/O
17
- I/O
24
, and BW4 controls I/O
25
- I/O
32
, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
A63L73321
PRELIMINARY (August, 2000, Version 0.4)
2
AMIC Technology, Inc.
Pin Configuration
NC
I/O
17
I/O
18
VCCQ
GNDQ
I/O
19
I/O
20
I/O
21
I/O
22
GNDQ
I/O
23
I/O
24
VCCQ
VCC
NC
I/O
31
GND
I/O
25
I/O
26
VCCQ
GNDQ
I/O
27
I/O
28
I/O
29
I/O
30
GNDQ
VCCQ
I/O
32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
30
27
29
80
79
78
77
76
75
74
72
73
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
16
I/O
15
VCCQ
GNDQ
I/O
14
I/O
13
I/O
12
I/O
11
GNDQ
VCCQ
I/O
10
I/O
9
GND
NC
VCC
ZZ
I/O
8
I/O
7
VCCQ
GNDQ
I/O
6
I/O
5
I/O
4
I/O
3
GNDQ
VCCQ
I/O
2
I/O
1
NC
50
49
48
47
46
45
44
43
42
40
41
39
38
37
36
35
34
33
32
31
A16
A15
A14
A13
A12
A11
A10
NC
NC
VCC
GND
NC
NC
A0
A1
A2
A3
A4
A5
MODE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CE2
A7
A6
CLK
GND
VCC
A9
A8
A63L73321E
NC
ADV
ADSP
ADSC
OE
BWE
GW
CE2
BW1
BW2
BW3
BW4
CE
x
A63L73321
PRELIMINARY (August, 2000, Version 0.4)
3
AMIC Technology, Inc.
Block Diagram
MODE
LOGIC
CLK
LOGIC
ADDRESS
REGISTERS
BURST
LOGIC
ADDRESS
COUNTER
CLR
BYTE
WRITE
ENABLE
LOGIC
BYTE1
WRITE
DRIVER
BYTE2
WRITE
DRIVER
BYTE3
WRITE
DRIVER
BYTE4
WRITE
DRIVER
8
8
8
8
128KX8X4
MEMORY
ARRAY
8
8
8
8
32
OUTPUT
BUFFER
DATA-IN
REGISTERS
4
CHIP
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
4
32
17
ZZ
MODE
ADV
CLK
ADSC
ADSP
A0-A16
GW
BWE
BW1
BW2
BW3
BW4
CE
CE2
CE2
OE
I/O
1
- I/O
32
A63L73321
PRELIMINARY (August, 2000, Version 0.4)
4
AMIC Technology, Inc.
Pin Description
Pin No.
Symbol
Description
32 - 37, 44 - 50, 81, 82,
99, 100
A0 - A16
Address Inputs
89
CLK
Clock
87, 93 - 96
BWE , BW1 - BW4
Byte Write Enables
88
GW
Global Write
86
OE
Output Enable
92, 97, 98
CE2 ,CE2, CE
Chip Enables
83
ADV
Burst Address Advance
84
ADSP
Processor Address Status
85
ADSC
Controller Address Status
31
MODE
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64
ZZ
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
2, 3, 6 - 9, 12, 13, 18, 19,
22 - 25, 28, 29, 52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79
I/O
1
- I/O
32
Data Inputs/Outputs
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
NC
No Connection
15, 41, 65, 91
VCC
Power Supply
17, 40, 67, 90
GND
Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ
Isolated Output Buffer Ground
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