A63L83361
256K X 36 Bit Synchronous High Speed SRAM with
Preliminary
Burst Counter and Flow-through Data Output
PRELIMINARY (July, 2005, Version 0.0)
AMIC Technology, Corp.
Document Title
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-
through Data Output
Revision History
Rev. No. History Issue
Date Remark
0.0
Initial issue
July 14, 2005
Preliminary
A63L83361
256K X 36 Bit Synchronous High Speed SRAM with
Preliminary
Burst Counter and Flow-through Data Output
PRELIMINARY (July, 2005, Version 0.0)
1
AMIC Technology, Corp.
Features
Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)
Single 3.3V
5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Industrial operating temperature range: -45
C to
+125
C for -I series
General Description
The A63L83361 is a high-speed SRAM containing 9M bits
of bit synchronous memory, organized as 256K words by
36 bits.
The A63L83361 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 256K X 36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A17), all data inputs (I/O
1
- I/O
36
), active LOW chip
enable (
CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global
Write ( GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L83361
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
A63L83361
PRELIMINARY (July, 2005, Version 0.0)
4
AMIC Technology, Corp.
Pin Description
Pin No.
Symbol
Description
32 37 , 43 - 50, 81, 82,
99, 100
A0 - A17
Address Inputs
89 CLK
Clock
87, 93 - 96
BWE , BW1 - BW4
Byte Write Enables
88
GW
Global Write
86
OE
Output Enable
92, 97, 98
CE2 ,CE2, CE
Chip Enables
83
ADV
Burst Address Advance
84
ADSP
Processor Address Status
85
ADSC
Controller Address Status
31
MODE
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64
ZZ
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,30,51,
52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
I/O
1
- I/O
36
Data
Inputs/Outputs
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
NC No
Connection
15, 41, 65, 91
VCC
Power Supply
17, 40, 67, 90
GND
Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ
Isolated Output Buffer Ground
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