A67L1618/A67L0636 Series

Preliminary

2M X 18, 1M X 36 LVTTL, Pipelined ZeBL

SRAM

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Features

Fast access time:

2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)

Zero Bus Latency between READ and WRITE cycles
allows 100% bus utilization

Signal +3.3V

5% power supply

Individual Byte Write control capability

Clock enable (

CEN

) pin to enable clock and suspend

operations

Clock-controlled and registered address, data and control

signals

Registered output for pipelined applications

Three separate chip enables allow wide range of options
for CE control, address pipelining

Internally self-timed write cycle

Selectable BURST mode (Linear or Interleaved)

SLEEP mode (ZZ pin) provided

Available in 100 pin LQFP package

General Description

The AMIC Zero Bus Latency (ZeBL

) SRAM family employs

high-speed, low-power CMOS designs using an advanced
CMOS process.
The A67L1618, A67L0636 SRAMs integrate a 2M X 18, 1M
X 36 SRAM core with advanced synchronous peripheral
circuitry and a 2-bit burst counter. These SRAMs are
optimized for 100 percent bus utilization without the insertion
of any wait cycles during Write-Read alternation. The positive
edge triggered single clock input (CLK) controls all
synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs, active
low chip enable (

), two additional chip enables for easy

depth expansion (CE2,

CE2

), cycle start input (ADV/ LD ),

synchronous clock enable (

CEN

), byte write enables

(

BW1

BW2

BW3

BW4

) and read/write (R/

Asynchronous inputs include the output enable (

), clock

(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/ LD ) pin in Low

state. Subsequent burst address can be internally generated
by the chip and controlled by the same input pin ADV/LD in

High state.

Write cycles are internally self-time and synchronous with the
rising edge of the clock input and when R/

is Low. The

feature simplified the write interface. Individual Byte enables
allow individual bytes to be written.

BW1

controls I/Oa pins;

BW2

controls I/Ob pins;

BW3

controls I/Oc pins; and

BW4

controls I/Od pins. Cycle types can only be defined when an
address is loaded.
The SRAM operates from a +3.3V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Pin Configuration

17
18

A20

2M x 18

MODE

1M x 36

I/Ob

I/Oa

A19

A18

A10

VCCQ

VSSQ

VCCQ

VSS

VCC

VCCQ

VSSQ

VCCQ

I/Oa

VCCQ

VSSQ

VCCQ

VCC

VSS

VCCQ

VSSQ

VCCQ

I/Ob

VCC

I/Ob

CLK

VCCQ

VSSQ

VCCQ

VSS

VCC

VCCQ

VSSQ

VCCQ

I/Ob

BW4

BW3

BW2

BW1

A67L1618E
A67L0636E

I/Ob

VCCQ

VSSQ

VCCQ

VCC

VSS

VCCQ

VSSQ

VCCQ

VCC

I/Oc

I/Od

I/Oa

I/Ob

I/Oa

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Block Diagram (1M X 36)

1M x 9 x 4

MEMORY

ARRAY

MODE

LOGIC

CLK

LOGIC

ADDRESS

REGISTERS

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

REGISTRY

CONTROL

LOGIC

BYTEa
WRITE
DRIVER

BYTEb
WRITE
DRIVER

BYTEc
WRITE
DRIVER

BYTEd
WRITE
DRIVER

OUTPUT

REGISTERS

OUTPUT

BUFFERS

DATA-IN

REGISTERS

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

OUTPUT

ENABLE

LOGIC

MODE

ADV/LD

CLK

A0-A19

R/W

BW1
BW2
BW3
BW4

CE2
CE2

CEN

WRITE

ADDRESS

WRITE

ADDRESS

ADV/LD

DATA-IN

REGISTERS

I/O

SENSE

AMPS

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Block Diagram (2M X 18)

DATA-IN

REGISTERS

MODE

LOGIC

CLK

LOGIC

ADDRESS

REGISTERS

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

REGISTRY

CONTROL

LOGIC

BYTEa
WRITE
DRIVER

BYTEb
WRITE
DRIVER

2M X 9 X 2

MEMORY

ARRAY

OUTPUT

REGISTERS

OUTPUT

BUFFERS

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

OUTPUT

ENABLE

LOGIC

MODE

ADV/LD

CLK

A0-A20

R/W
BW1

BW2

CE2
CE2

CEN

WRITE

ADDRESS

WRITE

ADDRESS

ADV/LD

I/O

SENSE

AMPS

DATA-IN

REGISTERS

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Pin Description

Pin No.

Symbol

Description

LQFP (X18)

LQFP (X36)

37
36

35, 34, 33, 32,

100, 99, 82, 81,

44, 45, 46, 47,

48, 49, 50, 83, 84

43
80

37
36

35, 34, 33, 32,

100, 99, 82, 81,

45, 46, 47, 48,

49, 50, 83, 84, 43

A0
A1

A2 - A9

A11 - A19

A20
A10

Synchronous Address Inputs : These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two lest significant bits (LSB) of the
address field and set the internal burst counter if burst is desired.

93 (

BW1

)

94 (

BW2

)

93 (

BW1

)

94 (

BW2

)

95 (

BW3

)

96 (

BW4

)

BW1

BW2

BW3

BW4

Synchronous Byte Write Enables : These active low inputs allow
individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of
CLK. BYTE WRITEs need to be asserted on the same cycle as
the address, BWs are associated with addresses and apply to
subsequent data.

BW1

controls I/Oa pins;

BW2

controls I/Ob pins;

BW3

controls I/Oc pins;

BW4

controls I/Od pins.

89 89

CLK

Clock: This signal registers the address, data, chip enables, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock are rising edge.

98 98

Synchronous Chip Enable : This active low input is used to enable
the device. This input is sampled only when a new external
address is loaded (ADV/LD LOW).

92 92

CE2

Synchronous Chip Enable : This active low input is used to enable
the device and is sampled only when a new external address is
loaded (ADV/LD LOW). This input can be used for memory depth
expansion.

CE2

Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used for
memory depth expansion.

86 86

Output Enable : This active low asynchronous input enables the
data I/O output drivers.

85 85

ADV/LD

Synchronous Address Advance/Load : When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When HIGH, R/

ignored. A LOW on this pin permits a new address to be loaded at
CLK rising edge.

87 87

CEN

Synchronous Clock Enable : This active low input permits CLK to
propagate throughout the device. When HIGH, the device ignores
the CLK input and effectively internally extends the previous CLK
cycle. This input must meet setup and hold times around the
rising edge of CLK.

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Pin Description (continued)

Pin No.

Symbol

Description

LQFP (X18)

LQFP (X36)

Snooze Enable : This active high asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When active, all other inputs are
ignored.

88 88

Read/Write : This active input determines the cycle type when
ADV/LD is LOW. This is the only means for determining READs
and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on
this pin permits BYTE WRITE operations and must meet the setup
and hold times around the rising edge of CLK. Full bus width
WRITEs occur if all byte write enables are LOW.

74, 73, 72, 69, 68,

63, 62, 59, 58,

24, 23, 22, 19, 18

13, 12, 9, 8

51, 52, 53, 56, 57,

58, 59, 62, 63

68, 69, 72, 73, 74,

75, 78, 79, 80

1, 2, 3, 6, 7, 8, 9,

12, 13,

18, 19, 22, 23, 24,

25, 28, 29, 30

I/Oa

I/Ob

I/Oc

I/Od

SRAM Data I/O : Byte "a" is I/Oa pins; Byte "b" is I/Ob pins; Byte
"c" is I/Oc pins; Byte "d" is I/Od pins. Input data must meet setup
and hold times around CLK rising edge.

31 31

MODE

Mode : This input selects the burst sequence. A LOW on this pin
selects linear burst. NC or HIGH on this pin selects interleaved
burst. Do not alter input state while device is operating.

1, 2, 3, 6, 7, 25, 28,

29, 30, 38, 39, 42,
51, 52, 53, 56, 57,

75, 78, 79, 95, 96

38,39,42

No Connect : These pins can be left floating or connected to GND
to minimize thermal impedance.

15, 41, 65, 91

VCC

Power Supply : See DC Electrical Characteristics and Operating
Conditions for range.

14, 16, 66

VCC

These pins do not have to be connected directly to VCC as long
as the input voltage is

. This input is not connected to VCC

bus internally.

4, 11, 20, 27,

54, 61, 70, 77

4, 11, 20, 27, 54,

61, 70, 77

VCCQ

Isolated Output Buffer Supply : See DC Electrical Characteristics
and Operating Conditions for range.

17, 40, 90

VSS

Ground : GND.

5,10,21,26,

55,60,71,76

5,10,21,26,

55,60,71,76

VSSQ

Isolated Output Buffer Ground

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Truth Table (Notes 5 - 7)

Operation

Address

Used

CE2

ADV/

BWx

CEN

CLK I/O Notes

Deselected Cycle,
Power-down

None H

X X L L X X X L L

H High-Z

Deselected Cycle,
Power-down

None X

H X L L X X X L L

H High-Z

Deselected Cycle,
Power-down

None X

X L L L X X X L L

H High-Z

Continue Deselect
Cycle

None X

X X L H X X X L L

H High-Z

READ Cycle
(Begin Burst)

External

L L H L L H X L L L

H Q

READ Cycle
(Continue Burst)

Next X

X X L H X X L L

H Q 1,7

NOP/Dummy READ
(Begin Burst)

External

L L H L L H X H L L

H High-Z

Dummy READ
(Continue Burst)

Next X

X X L H X X H L

H High-Z

1,2,7

WRITE Cycle
(Begin Burst)

External

L H L L L L X L

H D

WRITE Cycle
(Continue Burst)

Next X

X X L H X L X L

H D 1,3,7

NOP/WRITE Abort
(Begin Burst)

None L L H L L L H X L

H High-Z

2,3

WRITE Abort
(Continue Burst)

Next X

X X L H X H X L

H High-Z

1,2,3,7

IGNORE Clock Edge
(Stall)

Current X X X L X X X X H L

H -

SLEEP Mode

None

High-Z

Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.

2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE

Abort means a WRITE command is given, but no operation is performed.

3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the

output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.

4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during

a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle.

5. X means "Don't Care." H means logic HIGH. L means logic LOW.

BWx

= H means all byte write signals (

BW1

BW2

BW3

and

BW4

) are HIGH.

BWx

= L means one or more byte write signals are LOW.

BW1

enables WRITEs to Byte "a" (I/Oa pins);

BW2

enables WRITEs to Byte "b" (I/Ob pins);

BW3

enables WRITEs to Byte

"c" (I/Oc pins);

BW4

enables WRITEs to Byte "d" (I/Od pins).

7. The address counter is incremented for all Continue Burst cycles.

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Partial Truth Table for READ/WRITE Commands (X18)

Operation R/

BW1

BW2

READ H

WRITE Byte "a"

WRITE Byte "b"

WRITE all bytes

WRITE Abort/NOP

Note : Using and BYTE WRITE(s), any one or more bytes may be written.

Partial Truth Table for READ/WRITE Commands (X36)

Operation R/

BW1

BW2

BW3

BW4

READ

H X X X X

WRITE Byte "a"

WRITE Byte "b"

WRITE Byte "c"

WRITE Byte "d"

WRITE all bytes

WRITE

Abort/NOP

L H H H H

Note : Using R/

and BYTE WRITE(s), any one or more bytes may be written.

Linear Burst Address Table (MODE = LOW)

First Address (External) Second

Address

(Internal)

Third Address (Internal)

Fourth Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

Interleaved Burst Address Table (MODE = HIGH or NC)

First Address (External) Second

Address

(Internal)

Third Address (Internal)

Fourth Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Absolute Maximum Ratings*

Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature (Topr) . . . . . . . . . . . 0

C to 70

Storage Temperature (Tbias) . . . . . . . . . . -10

C to 85

Storage Temperature (Tstg) . . . . . . . . . . -55

C to 125

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics and Operating Conditions

C, VCC, VCCQ = +3.3V

5% unless otherwise noted)

Symbol Parameter

Conditions

Min.

Max.

Unit

Note

Input High Voltage

2.0

VCC+0.3

1,2

Input Low Voltage

-0.3

0.8

1,2

Input Leakage Current

VCC

-2.0

TBD

Output Leakage Current

Output(s) disabled,

VCC

-2.0 TBD

Output High Voltage

= -4.0mA

2.4

1,3

Output Low Voltage

= 8.0mA

0.4

1,3

VCC Supply

Voltage

3.135 3.465

VCCQ

Isolated Output Buffer Supply

3.135

VCC

1,4

Capacitance

Symbol Parameter

Conditions

Typ.

Max.

Unit

Note

Control Input Capacitance

Input/Output Capacitance (I/O)

Address

Capacitance

= 25

C; f = 1MHz

VCC = 3.3V

3 3.5 pF 6

Note : 1. All voltages referenced to VSS (GND).

2. Overshoot : V

+4.6V for t

KHKH

/2 for I

20mA

Undershoot : V

-0.7V for t

KHKH

/2 for I

20mA

Power-up :

+3.456V and VCC

3.135V for t

200ms

3. The load used for V

, V

testing is shown in Figure 2. AC load current is higher than the shown DC values.

AC I/O curves are available upon request.
4. VCC and VCCQ can be externally wired together to the same power supply.
5. This parameter is sampled.

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Operating Condition and Maximum Limits

Max.

Symbol Parameter

-2.6 -2.8 -3.2

-3.5

-3.8

-4.2

Unit

Conditions

Power Supply
Current : Operating

460 440 410

360

330

310

Device selected; All inputs

; Cycle time

(MIN); VCC =

MAX; Outputs open

Standby

TBD TBD TBD

TBD

Device deselected; VCC = MAX;
All inputs

VSS+0.2 or

VCC-0.2;

Cycle time

(MIN)

SB1

Standby

TBD TBD TBD

TBD

Device deselected; VCC = MAX;
All inputs

VSS+0.2 or

VCC-0.2;

All inputs static; CLK frequency=0
ZZ

0.2V

SB2

Standby

TBD TBD TBD

TBD

Device deselected; VCC = MAX;
All inputs

; or

; All

inputs static;

CLK frequency=MAX

VCC-0.2V

SB2Z

SLEEP

Mode

TBD TBD TBD

TBD

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

AC Characteristics

(Note 4)

C, VCC = +3.3V

5%)

-2.6 -2.8 -3.2 -3.5 -3.8 -4.2

Unit

Note

Symbol Parameter

Min Max Min

Max

Min

Max

Min

Max

Min

Max Min Max

Clock

KHKH

Clock cycle time

4.0

4.4

5.0

6.0

6.7

7.5

Clock

frequency

- 250 - 227

- 200

- 166

- 150 - 133 MH

KHKL

Clock HIGH time

1.7

2.0

2.2

2.5

3.0

KLKH

Clock LOW time

1.7

2.0

2.2

2.5

3.0

Output Times

KHQV

Clock to output valid

2.6

2.8

3.2

3.5

3.8

4.2

KHQX

Clock to output invalid

1.5

KHQX1

Clock to output in Low-Z

1.5

1,2,3

KHQZ

Clock to output in High-Z

1.5

2.6

1.5

2.8

1.5

3.0

1.5

3.0

1.5

3.0

1.5

3.5

1,2,3

GLQV

to output valid

- 2.6 - 2.8

- 3.2

- 3.5

- 3.8 - 4.2 ns

GLQX

to output in Low-Z

0 - 0 - 0 - 0 - 0 - 0 - ns

1,2,3

GHQZ

to output in High-Z

- 2.6 - 2.8

- 3.0

- 3.0 - 3.5 ns

1,2,3

Setup Times

AVKH

Address

1.2 - 1.4

- 1.4

- 1.5

- 1.5 - ns

EVKH

Clock enable (

CEN

)

1.2 - 1.4

- 1.4

- 1.5

- 1.5 - ns

CVKH

Control

signals

1.2 - 1.4

- 1.4

- 1.5

- 1.5 - ns

DVKH

Data-in

1.2 - 1.4

- 1.4

- 1.5

- 1.5 - ns

Hold Times

KHAX

Address

0.3 - 0.4

- 0.4

- 0.5

- 0.5 - ns

KHEX

Clock enable (

CEN

)

0.3 - 0.4

- 0.4

- 0.5

- 0.5 - ns

KHCX

Control

signals

0.3 - 0.4

- 0.4

- 0.5

- 0.5 - ns

KHDX

Data-in

0.3 - 0.4

- 0.4

- 0.5

- 0.5 - ns

Notes: 1. This parameter is sampled.

2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured

200mV from steady state voltage.

4. OE can be considered a "Don't Care" during WRITE; however, controlling OE can help fine-tune a system for

turnaround timing.

5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic
levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of
CLK (when ADV/LD is LOW) to remain enabled.

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

SLEEP Mode

SLEEP Mode is a low current "Power-down" mode in which the
device is deselected and current is reduced to I

SB2Z

. This

duration of SLEEP Mode is dictated by the length of time the
ZZ is in a HIGH state. After entering SLEEP Mode, all inputs
except ZZ become disabled and all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes the
device to enter SLEEP Mode. When the ZZ pin becomes
logic HIGH, ISB2Z is guaranteed after the time t

ZZI

is met.

Any operation pending when entering SLEEP Mode is not
guaranteed to successfully complete. Therefore, SLEEP
Mode (READ or WRITE) must not be initiated until valid
pending operations are completed. Similarly, when exiting
SLEEP Mode during t

RZZ

, only a DESELECT or READ cycle

should be given while the SRAM is transitioning out of
SLEEP Mode.

SLEEP Mode Electrical Characteristics

(VCC, VCCQ = +3.3V

5%)

Symbol Parameter

Conditions

Min.

Max.

Unit

Note

SB2Z

Current during SLEEP Mode

ZZ active to input ignored

2(t

KHKH

) ns

RZZ

ZZ inactive to input sampled

2(t

KHKH

) ns

ZZI

ZZ active to snooze current

- 2(t

KHKH

) ns

RZZI

ZZ inactive to exit snooze current

Note : 1. This parameter is sampled.

SLEEP Mode Waveform

RZZ

ZZI

ISB2Z

High-Z

DESELECT or READ Only

Output

(Q)

ALL INPUTS

(except ZZ)

SUPPLY

CLK

: Don't Care

RZZI

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

READ/WRITE Timing

Note :

1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3.

represents three signals. When

= 0, it represents

= 0,

CE2

= 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most

recent data may be from the input data register.

D(A1)

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

: Don't Care

: Undefined

GLQX

KHKH

CLK

CEN

ADV/

R/W

BWx

ADDRESS

I/O

COMMAND

D(A2)

D(A2+1)

Q(A6)

D(A5)

Q(A4+1)

Q(A4)

Q(A3)

KLKH

EVKH

KHEX

KHKL

KHCX

CVKH

KHAX

AVKH

KHDX

DVKH

KHQZ

GLQV

KHQX

GHQZ

KHQX

KHQV

KHQX1

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

NOP, STALL and Deselect Cycles

Note :

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates

CEN

being used to create a "pause." A WRITE is not

performed during this cycle.

2. For this waveform, ZZ and

are tied LOW.

represents three signals. When

= 0, it represents

= 0,

= 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

Q(A5)

D(A4)

Q(A3)

Q(A2)

D(A1)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

: Don't Care

: Undefined

KHQX

KHQZ

CLK

CEN

ADV/

R/W

BWx

ADDRESS

I/O

COMMAND

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Ordering Information

Part No.

Configure

Cycle Time / Access Time

Package

A67L1618E-4.2

7.5ns / 4.2ns

100L LQFP

A67L1618E-4.2F

7.5ns / 4.2ns

100L Pb-Free LQFP

A67L1618E-3.8

6.7ns / 3.8ns

100L LQFP

A67L1618E-3.8F

6.7ns / 3.8ns

100L Pb-Free LQFP

A67L1618E-3.5

6.0ns / 3.5ns

100L LQFP

A67L1618E-3.5F

6.0ns / 3.5ns

100L Pb-Free LQFP

A67L1618E-3.2

5.0ns / 3.2ns

100L LQFP

A67L1618E-3.2F

5.0ns / 3.2ns

100L Pb-Free LQFP

A67L1618E-2.8

4.4ns / 2.8ns

100L LQFP

A67L1618E-2.8F

4.4ns / 2.8ns

100L Pb-Free LQFP

A67L1618E-2.6

4.0ns / 2.6ns

100L LQFP

A67L1618E-2.6F

2M X 18

4.0ns / 2.6ns

100L Pb-Free LQFP

A67L0636E-4.2

7.5ns / 4.2ns

100L LQFP

A67L0636E-4.2F

7.5ns / 4.2ns

100L Pb-Free LQFP

A67L0636E-3.8

6.7ns / 3.8ns

100L LQFP

A67L0636E-3.8F

6.7ns / 3.8ns

100L Pb-Free LQFP

A67L0636E-3.5

6.0ns / 3.5ns

100L LQFP

A67L0636E-3.5F

6.0ns / 3.5ns

100L Pb-Free LQFP

A67L0636E-3.2

5.0ns / 3.2ns

100L LQFP

A67L0636E-3.2F

5.0ns / 3.2ns

100L Pb-Free LQFP

A67L0636E-2.8

4.4ns / 2.8ns

100L LQFP

A67L0636E-2.8F

4.4ns / 2.8ns

100L Pb-Free LQFP

A67L0636E-2.6

4.0ns / 2.6ns

100L LQFP

A67L0636E-2.6F

1M X 36

4.0ns / 2.6ns

100L Pb-Free LQFP

A67L1618/A67L0636 Series

PRELIMINARY (March, 2005, Version 0.1)

AMIC Technology, Corp.

Package Information

LQFP 100L Outline Dimensions

unit: inches/mm

Symbol

Dimensions in inches

Dimensions in mm

Min.

Nom.

Max.

Min.

Nom.

Max.

0.002

- - 0.05 - -

0.053

0.055

0.057

1.35

1.40

1.45

b 0.011

0.013

0.015

0.27

0.32

0.37

c 0.005

0.008

0.12 - 0.20

0.860

0.866

0.872

21.85

22.00

22.15

E 0.783

0.787

0.791

19.90

20.00

20.10

0.624

0.630

0.636

15.85

16.00

16.15

D 0.547

0.551

0.555

13.90

14.00

14.10

0.026 BSC

0.65 BSC

L 0.018

0.024

0.030

0.45

0.60

0.75

0.039 REF

1.00 REF

y -

0.004

0.1

3.5

Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.

Total in excess of the b dimension at maximum material condition.

Dambar cannot be located on the lower radius of the foot.

100

D y

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A67L0636E-4.2F