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Электронный компонент: A67P9336E-3.5F

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A67P0618/A67P9336 Series
Preliminary
1M X 18, 512K X 36 LVTTL, Pipelined ZeBL
TM
SRAM
PRELIMINARY (March, 2006, Version 0.2)
AMIC Technology, Corp.
Document Title
1M X 18, 512K X 36 LVTTL, Pipelined ZeBL
TM
SRAM
Revision History
Rev. No. History Issue
Date Remark
0.0 Initial
issue
September, 20, 2004
Preliminary
0.1
Add Pb-Free package type.
January 27, 2006
0.2
Modify DC specification to exact value
March 2, 2006
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A67P0618/A67P9336 Series
Preliminary
1M X 18, 512K X 36 LVTTL, Pipelined ZeBL
TM
SRAM
PRELIMINARY (March, 2006, Version 0.2)
2
AMIC Technology, Corp.
Features
Fast access time:
2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
Zero Bus Latency between READ and WRITE cycles
allows 100% bus utilization
Signal +2.5V
5% power supply
Individual Byte Write control capability
Clock enable (
CEN
) pin to enable clock and suspend
operations
Clock-controlled and registered address, data and
control signals
Registered output for pipelined applications
Three separate chip enables allow wide range of
options for CE control, address pipelining
Internally self-timed write cycle
Selectable BURST mode (Linear or Interleaved)
SLEEP mode (ZZ pin) provided
Available in 100 pin LQFP package

General Description

The AMIC Zero Bus Latency (ZeBL
TM
) SRAM family
employs high-speed, low-power CMOS designs using an
advanced CMOS process.
The A67P0618, A67P9336 SRAMs integrate a 1M X 18,
512K X 36 SRAM core with advanced synchronous
peripheral circuitry and a 2-bit burst counter. These SRAMs
are optimized for 100 percent bus utilization without the
insertion of any wait cycles during Write-Read alternation.
The positive edge triggered single clock input (CLK) controls
all synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs,
active low chip enable (
CE
), two additional chip enables for
easy depth expansion (CE2,
CE2
), cycle start input
(ADV/ LD ), synchronous clock enable (
CEN
), byte write
enables (
BW1
,
BW2
,
BW3
,
BW4
) and read/write (R/
W
).
Asynchronous inputs include the output enable (
OE
), clock
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/LD ) pin in Low
state. Subsequent burst address can be internally
generated by the chip and controlled by the same input pin
ADV/LD in High state.
Write cycles are internally self-time and synchronous with
the rising edge of the clock input and when R/
W
is Low.
The feature simplified the write interface. Individual Byte
enables allow individual bytes to be written.
BW1
controls
I/Oa pins;
BW2
controls I/Ob pins;
BW3
controls I/Oc pins;
and
BW4
controls I/Od pins. Cycle types can only be
defined when an address is loaded.
The SRAM operates from a +2.5V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
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A67P0618/A67P9336 Series
PRELIMINARY (March, 2006, Version 0.2)
3
AMIC Technology, Corp.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
30
27
29
80
79
78
77
76
75
74
72
73
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
40
41
39
38
37
36
35
34
33
32
31
A1
7
A1
6
A1
5
A1
4
A1
3
A1
2
A1
1
NC
VC
C
VS
S
NC
NC
A0
A1
A2
A3
A4
A5
MOD
E
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1M x 18
A16
A15
A14
A13
A12
A11
A1
0
VCC
VS
S
NC
A0
A1
A2
A3
A4
A5
MO
D
E
512K x 36
I/Ob
8
I/Oa
8
NC
NC
A6
A7
CE
2
NC
NC
VC
C
VS
S
CL
K
A1
9
A1
8
A8
A9
A10
NC
NC
VCCQ
VSSQ
NC
VSSQ
VCCQ
VSS
VCC
VCC
ZZ
VCCQ
VSSQ
NC
NC
VSSQ
VCCQ
NC
NC
NC
I/Oa
0
I/Oa
1
NC
NC
NC
VCCQ
VSSQ
NC
NC
VSSQ
VCCQ
VCC
VCC
VSS
VCCQ
VSSQ
NC
VSSQ
VCCQ
NC
NC
NC
I/Ob
8
I/Ob
7
I/Ob
6
VCC
I/Ob
4
CE
2
A7
A6
CLK
VS
S
VC
C
A9
A8
A1
8
A1
7
VCCQ
VSSQ
VSSQ
VCCQ
VSS
VCC
VCC
ZZ
VCCQ
VSSQ
VSSQ
VCCQ
I/Ob
7
CE
CE
BW
4
BW
3
BW
2
BW
2
BW
1
BW
1
CE
2
CE
2
CE
N
CE
N
OE
OE
AD
V
/
LD
AD
V
/
LD
A67P0618E
A67P9336E
R/
W
R/
W
I/Ob
5
I/Ob
3
I/Ob
2
I/Ob
1
I/Ob
0
VCCQ
VSSQ
VSSQ
VCCQ
VCC
VCC
VSS
VCCQ
VSSQ
VSSQ
VCCQ
VCC
I/Oc
8
I/Oc
0
I/Oc
1
I/Oc
2
I/Oc
3
I/Oc
4
I/Oc
5
I/Oc
6
I/Oc
7
I/Od
0
I/Od
1
I/Od
2
I/Od
3
I/Od
4
I/Od
5
I/Od
6
I/Od
7
I/Od
8
I/Oa
2
I/Oa
3
I/Oa
4
I/Oa
5
I/Oa
6
I/Oa
7
I/Oa
8
I/Ob
6
I/Ob
5
I/Ob
4
I/Ob
3
I/Ob
2
I/Ob
1
I/Ob
0
I/Oa
7
I/Oa
6
I/Oa
5
I/Oa
4
I/Oa
3
I/Oa
2
I/Oa
1
I/Oa
0
NC
NC
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A67P0618/A67P9336 Series
PRELIMINARY (March, 2006, Version 0.2)
4
AMIC Technology, Corp.
Block Diagram (512K X 36)
512K x 9 x 4
MEMORY
ARRAY
MODE
LOGIC
CLK
LOGIC
ADDRESS
REGISTERS
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
REGISTRY
&
CONTROL
LOGIC
BYTEa
WRITE
DRIVER
BYTEb
WRITE
DRIVER
BYTEc
WRITE
DRIVER
BYTEd
WRITE
DRIVER
9
9
9
9
9
9
9
9
OUTPUT
REGISTERS
&
OUTPUT
BUFFERS
DATA-IN
REGISTERS
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
ZZ
MODE
ADV/LD
CLK
A0-A18
R/W
BW1
BW2
BW3
BW4
CE
CE2
CE2
OE
CEN
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
ADV/LD
DATA-IN
REGISTERS
I/O
s
SENSE
AMPS
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A67P0618/A67P9336 Series
PRELIMINARY (March, 2006, Version 0.2)
5
AMIC Technology, Corp.
Block Diagram (1M X 18)
DATA-IN
REGISTERS
MODE
LOGIC
CLK
LOGIC
ADDRESS
REGISTERS
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
REGISTRY
&
CONTROL
LOGIC
BYTEa
WRITE
DRIVER
BYTEb
WRITE
DRIVER
9
9
1M X 9 X 2
MEMORY
ARRAY
9
9
OUTPUT
REGISTERS
&
OUTPUT
BUFFERS
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
ZZ
MODE
ADV/LD
CLK
A0-A19
R/W
BW1
BW2
CE
CE2
CE2
OE
CEN
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
ADV/LD
I/O
S
SENSE
AMPS
DATA-IN
REGISTERS