A82DL32x4T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM
Preliminary
PRELIMINARY (August, 2005, Version 0.0)
1
AMIC Technology, Corp.
DISTINCTIVE CHARACTERISTICS
MCP Features
Single power supply operation 2.7 to 3.6 volt
High Performance
- Access time as fast as 70ns
Package 69-Ball TFBGA (8x11x1.4 mm)
Industrial operating temperature range: -40
C to 85
C
for U; -25
C to 85
C for I
Flash Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package
-
69-Ball TFBGA (8x11x1.4 mm)
Top or bottom boot block
Manufactured on 0.18 m process technology
- Compatible with AM42DL32x4G devices
Compatible with JEDEC standards
-
Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
-
Access time as fast as 70ns
-
Program time: 7s/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
-
2mA active read current at 1MHz
-
10mA active read current at 5MHz
-
200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125C
-
Reliable operation for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
-
Suspends erase operations to allow programming in
same bank
Data
Polling and Toggle Bit
-
Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
-
Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/
Busy
output (RY/
BY
)
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET )
- Hardware method of resetting the internal state machine
to reading array data
WP
/ACC input pin
- Write protect (
WP
) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
LP SRAM Features
Power supply range: 2.7V to 3.6V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 35mA(max.)
Standby: 10uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
Data retention voltage: 2.0V (min.)
A82DL32x4T(U) Series
PRELIMINARY (August, 2005, Version 0.0)
2
AMIC Technology, Corp.
GENERAL DESCRIPTION
The A82DL32x4T(U) family consists of 32 megabit, 3.0 volt-
only flash memory devices, organized as 2,097,152 words of
16 bits each or 4,194,304 bytes of 8 bits each. Word mode
data appears on I/O
0
I/O
15
; byte mode data appears on I/O
0
I/O
7
. The device is designed to be programmed in-system
with the standard 3.0 volt VCC supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 70ns. The
devices are offered in 69-ball Fine-pitch BGA. Standard
control pins--chip enable (
CE_F
), write enable (
WE
), and
output enable (
OE
)--control normal read and write
operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A82DL32x4T(U) devices uses multiple bank archi-
tectures to provide flexibility for different applications. Three
devices are available with these bank sizes:
Device
Bank 1
Bank 2
DL3224
4 Mb
28 Mb
DL3234
8 Mb
24 Mb
DL3244
16 Mb
16 Mb
A82DL32x4T(U) Features
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/
BY
pin, I/O
7
(
Data
Polling) and I/O
6
/I/O
2
(toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.
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