A83516 Series

Preliminary

8 Bit Microcontroller

PRELIMINARY (November,

1998, Version 0.0)

AMIC Technology, Inc.

Features

8-bit CMOS microcontroller

Fully static design with power saving idle mode and
power down mode

Low standby current at full supply voltage

Versions for 12/24/40MH

operating frequency

On chip 256B RAM

On chip 64KB X 8 MASK-ROM program memory

Four 8-bit bidirectional ports

Three 16-bit Timers/Counters (Timer 2 with up/down
counter feature)

One full duplex serial port

Boolean processor

Six interrupt sources, two priority levels

Available in 40-pin P-DIP and 44-pin PLCC packages

64K bytes external data memory space

General Description

The AMIC A83516 is a high-performance 8-bit
microcontroller. It is compatible with the industry
standard 80C52 microcontroller series.
The A83516 contains a 256B RAM, 64KB X 8 ROM, four
8-bit bidirectional parallel ports, three 16-bit

timer/counters, a serial port and six interrupt sources
with two priority levels.
The A83516 has two power reduction modes, idle mode
and power-down mode. It supports 64KB external data
memory.

Pin Configurations

P-DIP

PLCC

T2,P1.0

T2EX,P1.1

P1.2

TXD,P3.1

XTAL2
XTAL1

GND

P0.2,AD2

P0.1,AD1

P0.0,AD0

VCC

A83516

P0.3,AD3

P1.3
P1.4

P1.6

P1.7
RST

RXD,P3.0

T1,P3.5

INT0,P3.2

P1.5

PSEN

ALE

P0.7,AD7

P0.6,AD6

P0.5,AD5

P0.4,AD4

16
17

13
14
15

A83516L

P1.5

P1.4

INT1,P3.3

T0,P3.4

WR,P3.6

RD,P3.7

P2.7,A15
P2.6,A14
P2.5,A13
P2.4,A12
P2.3,A11
P2.2,A10
P2.1,A9
P2.0,A8

P1.3

P1.2

P1.1,T2EX

P1.0,T2

VCC

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

P1.6
P1.7

RST

RXD,P3.0

TXD,P3.1

INT0, P3.2

INT1,P3.3

T0,P3.4

T1,P3.5

P0.4,AD4

EA
NC
ALE

PSEN
P2.7,A15

P2.6,A14
P2.5,A13

38
37

36
35

34
33

32
31

30
29

7
8

9
10

11
12

13
14

16
17

P0.5,AD5
P0.6,AD6
P0.7,AD7

WR,P3.6

RD,P3.7

XTAL2

XTAL1

GND

P2.0,A8

P2.1,A9

P2.2,A10

P2.3,A11

P2.4,A12

A83516 Series

PRELIMINARY

(November, 1998, Version 0.0)

AMIC Technology, Inc.

Pin Description

Pin No.

P-DIP

PLCC

Symbol

Type

Description

I/O

Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin
P1.0 and P1.1 also provide alternate functions as follows:

I/O

P1.0

Timer/Counter2 external input/clock out

1 - 8

2 - 9

P1.0 - P1.7

P1.1

T2EX

Timer/Counter2 capture/reload input

RST

Reset input, active high. It must be kept high for at least two
machine cycles to be recognized by the processor

10 - 17

11,

13 - 19

P3.0 - P3.7

I/O

Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3
pins also serve alternate functions as follows:

P3.0

RXD

Serial receive port

P3.1

TXD

Serial transmit port

P3.2

INT0

External interrupt 0

P3.3

INT1

External interrupt 1

P3.4

Timer/Counter 0 input

P3.5

Timer/Counter 1 input

P3.6

External data memory write strobe

P3.7

External data memory read strobe

XTAL2

Crystal2. This is the output of crystal oscillator. It is the inversion
of XTAL1

XTAL1

Crystal1. This is the input of crystal oscillator. It can be driven by
an external clock

GND

Ground

21 - 28

24 - 31

P2.0 - P2.7

I/O

Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2
is also the multiplexed upper-order address bus during accesses
to external data memory

PSEN

Program Store Enable : active low. The read strobe to external
program memory.

PSEN

is activated in each machine cycle

when fetching external program memory

ALE

Address Latch Enable : active high. ALE is used to enable the
address latch that separates the data on Port 0

External Access Enable : active low. It is held low to enable the
device to fetch code from external program memory

32 - 39

36 - 43

P0.7 - P0.0

I/O

Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also
the multiplexed low-order address bus during accesses to external
data memory

VCC

Power supply

A83516 Series

PRELIMINARY

(November, 1998, Version 0.0)

AMIC Technology, Inc.

XTAL 2

XTAL 1
V

C1,C2 = 30pF � 10pF for Crystals

Figure 1. Oscillator Connections

XTAL 2

XTAL 1

N/C

EXTERNAL

OSCILLATOR

SIGNAL

Figure 2. External Clock Drive configuration

Functional Description

The A83516 is a high speed 8-bit microcontroller. The architecture consists of a core controller, four general purposes I/O
ports, 256 bytes RAM internal register, 64K bytes ROM and a serial port.
This microcontroller supports 111 opcodes and executes instructions in 12 clock/machine cycle. It can reference both a
64K program address space and a 64K data storage space.

Timer/Counter 0, 1 and 2

Timer 0,1 and 2 each consist of two 8-bit data registers.
These are called TL0 and TH0 for Timer 0. TL1 and TH1
for Timer 1, and TL2 and TH2 for Timer 2. The TMOD
and TCON registers support control function for Timer 0
and Timer 1. The T2CON register provides control
function for Timer 2. When operating reload/capture
mode, RCAP2H and RCAP2L will be used.

Interrupt

The A83516 provides 6 interrupt modes. These consist
of 2 external interrupts, 3 internal interrupts and a serial
port interrupt.
The enable/disable interrupt is controlled by IE register in
SFR.
The priority of interrupts is controlled by IP register in
SFR.

Serial Port Transfer

The A83516 provides a full duplex serial transfer
function.
This function is controlled by SCON register in SFR.
And the data is storaged in SBUF register during
transmitting and receiving.

Oscillator Characteristics

The oscillator connections are shown as Figure 1. And
Figure 2. When quartz crystal is used, C1 and C2 are
30pF shown in Figure 1. When external clock is used,
the internal clock will be gotten through a divide-by-two
flip-flop. When starting up, the input loading for XTAL1
pin is 100pF. This is due to interaction between the
amplifier and its feedback capacitance interaction. After
the external signal meets the V

and V

specification

the capacitance will not exceed 20pF.

Power Reduce Mode

IDLE Mode

It is executed by IDLE bit of PCON register in SFR. In
idle mode, the clock to microcontroller core is stopped.
The status in microcontroller core and I/O data are kept.
The microcontroller will stop idle status when either a
reset or an interrupt occurs.

POWER-DOWN Mode

It is executed by PD bit of PCON register in SFR. In
power-down mode, the oscillator clock will stop. The
data in RAM and status in SFR will be kept. The only
way to exit power-down mode is to reset this chip.

RESET

The external reset signal must be held high for at least
two machine cycles during the oscillator running.
After reset, the ports are held high, SP register to 07H,
all of the other SFR registers except SBUF to 00H, and
SBUF is not reset.

Электронный компонент: A83516-12