LP62S2048-I Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
Features
n
Power supply range: 2.7V to 3.3V
n
Access times: 70/100 ns (max.)
n
Current:
Low power version:
Operating: 30mA (max.)
Standby: 50
A (max.)
Very low power version: Operating: 30mA (max.)
Standby: 10
A (max.)
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL-compatible
n
Common I/O using three-state output
n
Output enable and two chip enable inputs for easy
application
n
Data retention voltage: 2V (min.)
n
Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
and 36-pin CSP packages
General Description
The LP62S2048-I is a low operating current 2,097,152-bit
static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
range: 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n
n
SOP
n
n
TSOP/(TSSOP)
n
n
CSP (Chip Size Package)
36-pin Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
LP62S2048M-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
LP62S2048V-I
(LP62S2048X-I)
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
CE2
A15
VCC
A17
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
CE1
WE
A0
I/O
5
I/O
6
GND
VCC
I/O
7
I/O
8
A9
A10
OE
A11
CE1
A12
A13
A14
A16
NC
A17
A15
I/O
4
I/O
3
I/O
2
I/O
1
GND
VCC
A1
A2
CE2
WE
NC
A5
A4
A3
A6
A7
A8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
LP62S2048-I Series
(August, 2001, Version 1.0)
2
AMIC Technology, Inc.
Block Diagram
ROW
DECODER
1024 X 2048
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
CE2
CE1
WE
I/O
8
I/O
1
A17
A16
A15
A0
VCC
GND
OE
Pin Description - SOP
Pin No.
Symbol
Description
1 - 12, 23,
25 - 28, 31
A0 - A17
Address Inputs
13 - 15,
17 - 21
I/O
1
- I/O
8
Data Input/Outputs
16
GND
Ground
22
CE1
Chip Enable
24
OE
Output Enable
29
WE
Write Enable
30
CE2
Chip Enable
32
VCC
Power Supply
Pin Descriptions - TSOP/TSSOP
Pin No.
Symbol
Description
1 - 4, 7,
9 - 20, 31
A0 - A17
Address Inputs
5
WE
Write Enable
6
CE2
Chip Enable
8
VCC
Power Supply
9
NC
No Connection
21 - 23,
25 - 29
I/O
1
- I/O
8
Data Input/Outputs
24
GND
Ground
30
CE1
Chip Enable
32
OE
Output Enable
LP62S2048-I Series
(August, 2001, Version 1.0)
3
AMIC Technology, Inc.
Pin Description - CSP
Symbol
Description
Symbol
Description
A0 - A17
Address Inputs
NC
No Connection
WE
Write Enable
I/O
1
- I/O
8
Data Input/Output
OE
Output Enable
VCC
Power Supply
CE1
Chip Enable
GND
Ground
CE2
Chip Enable
--
--
Recommended DC Operating Conditions
(T
A
= -40
C to + 85
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
2.7
3.0
3.3
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
-
VCC + 0.3
V
V
IL
Input Low Voltage
-0.3
-
+0.6
V
C
L
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
LP62S2048-I Series
(August, 2001, Version 1.0)
4
AMIC Technology, Inc.
Absolute Maximum Ratings*
VCC to GND . . . . . . . .. . . . . . . . . . . . . -0.5V to + 4.6V
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -40
C to + 85
C
Storage Temperature, Tstg . . .. . . . . . . -55
C to + 125
C
Temperature Under Bias, Tbias .. . . . . . -10
C to + 85
C
Power Dissipation, P
T
. . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260
C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics
(T
A
= -40
C to + 85
C, VCC = 2.7V to 3.3V, GND = 0V)
Symbol
Parameter
LP62S2048-70LI/10LI
LP62S2048-70LLI/10LLI
Unit
Conditions
Min.
Max.
Min.
Max.
I
LI
Input Leakage
Current
-
1
-
1
A
V
IN
= GND to VCC
I
LO
Output Leakage
Current
-
1
-
1
A
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
or WE = V
IL
V
I/O
= GND to VCC
I
CC
Active Power
Supply Current
-
3
-
3
mA
CE1 = V
IL
, CE2 = V
IH
I
I/O
= 0mA
I
CC1
Dynamic
Operating
-
30
-
30
mA
Min. Cycle, Duty = 100%
CE1 = V
IL
, CE2 = V
IH
I
I/O
= 0mA
I
CC2
Current
-
5
-
5
mA
CE1 = V
IL
, CE2 = V
IH
V
IH
= VCC, V
IL
= 0V
f = 1 MH
Z,
I
I/O
= 0mA
LP62S2048-I Series
(August, 2001, Version 1.0)
5
AMIC Technology, Inc.
DC Electrical Characteristics (continued)
Symbol
Parameter
LP62S2048-70LI/10LI
LP62S2048-70LLI/10LLI
Unit
Conditions
Min.
Max.
Min.
Max.
I
SB
-
0.5
-
0.5
mA
CE1 = V
IH
or CE2 =V
IL
I
SB1
Standby Power
Supply Current
-
50
-
10
A
CE1
VCC - 0.2V
V
IN
0V
I
SB2
-
50
-
10
A
CE2
0.2V
V
IN
0V
V
OL
Output Low
Voltage
-
0.4
-
0.4
V
I
OL
= 2.1mA
V
OH
Output High
Voltage
2.2
-
2.2
-
V
I
OH
= -1.0mA
Truth Table
Mode
CE1
CE2
OE
WE
I/O Operation
Supply Current
Standby
H
X
X
X
High Z
I
SB
, I
SB1
X
L
X
X
High Z
I
SB
, I
SB2
Output Disable
L
H
H
H
High Z
I
CC,
I
CC1,
I
CC2
Read
L
H
L
H
D
OUT
I
CC,
I
CC1,
I
CC2
Write
L
H
X
L
D
IN
I
CC,
I
CC1,
I
CC2
Note: X = H or L
Capacitance
(T
A
= 25
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
6
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
8
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
LP62S2048-I Series
(August, 2001, Version 1.0)
6
AMIC Technology, Inc.
AC Characteristics
(T
A
= -40
C to + 85
C, VCC = 2.7V to 3.3V)
Symbol
Parameter
LP62S2048-70LI/LLI
LP62S2048-10LI/LLI
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
70
-
100
-
ns
t
AA
Address Access Time
-
70
-
100
ns
t
ACE1
Chip Enable Access Time
CE1
-
70
-
100
ns
t
ACE2
CE2
-
70
-
100
ns
t
OE
Output Enable to Output Valid
-
35
-
50
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
10
-
10
-
ns
t
CLZ2
CE2
10
-
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
0
25
0
35
ns
t
CHZ2
CE2
0
25
0
35
ns
t
OHZ
Output Disable to Output in High Z
0
25
0
35
ns
t
OH
Output Hold from Address Change
10
-
10
-
ns
Write Cycle
t
WC
Write Cycle Time
70
-
100
-
ns
t
CW
Chip Enable to End of Write
60
-
80
-
ns
t
AS
Address Setup Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
60
-
80
-
ns
t
WP
Write Pulse Width
50
-
60
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
25
0
35
ns
t
DW
Data to Write Time Overlap
30
-
40
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
, and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
LP62S2048-I Series
(August, 2001, Version 1.0)
7
AMIC Technology, Inc.
Timing Waveforms
Read Cycle 1
(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
Read Cycle 2
(1, 3, 4, 6)
t
CLZ15
t
ACE1
t
CHZ15
CE1
D
OUT
Read Cycle 3
(1, 4, 7, 8)
t
CLZ25
t
ACE2
t
CHZ25
CE2
D
OUT
LP62S2048-I Series
(August, 2001, Version 1.0)
8
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 4
(1)
t
RC
Address
CE2
D
OUT
t
AA
t
OE
t
OLZ5
t
ACE1
t
CLZ15
t
ACE2
t
CLZ25
t
CHZ25
t
OHZ5
t
CHZ15
t
OH
OE
CE1
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = V
IL
and CE2 = V
IH
.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = V
IL
.
5. Transition is measured
500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
LP62S2048-I Series
(August, 2001, Version 1.0)
9
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
CE1
CE2
D
IN
t
OW
t
DH
t
DW
t
WHZ
t
WP2
t
AS1
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
(4)
LP62S2048-I Series
(August, 2001, Version 1.0)
10
AMIC Technology, Inc.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
CE1
CE2
D
IN
t
DH
t
DW
(4)
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
WP2
t
CW5
t
AS1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low CE1, a high CE2 and a low WE .
3. t
WR
is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. t
CW
is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = V
IL
)
7. Transition is measured
500mV from steady state. This parameter is sampled and not 100% tested.
LP62S2048-I Series
(August, 2001, Version 1.0)
11
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
30pF
* Including scope and jig.
* Including scope and jig.
C
L
TTL
5pF
C
L
TTL
Figure 1. Output Load
Figure 2. Output Load for t
CLZ1
,
t
CLZ2
, t
OHZ
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
WHZ
, and t
OW
Data Retention Characteristics
(T
A
= -40
C to 85
C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
DR1
2.0
3.3
V
CE1
VCC - 0.2V
V
DR2
VCC for Data Retention
2.0
3.3
V
CE2
0.2V,
I
CCDR1
L-Version
-
20*
A
VCC = 2.0V,
CE1
VCC - 0.2V,
Data Retention Current
LL-Version
-
5**
V
IN
0V
I
CCDR2
L-Version
-
20*
A
VCC = 2.0V,
CE2
0.2V,
LL-Version
-
5**
V
IN
0V
t
CDR
Chip Disable to Data Retention Time
0
-
ns
t
R
Operation Recovery Time
t
RC
-
ns
See Retention Waveform
t
VR
VCC Rising Time from Data Retention Voltage
to Operating Voltage
5
-
ms
** LP62S2048-70LLI/10LLI
I
CCDR
: max. 1
A at T
A
= 0
C to + 40
C
* LP62S2048-70LI/10LI
I
CCDR
: max. 5
A at T
A
= 0
C to + 40
C
LP62S2048-I Series
(August, 2001, Version 1.0)
12
AMIC Technology, Inc.
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
VCC
CE1
t
CDR
V
IH
2.7V
t
R
V
IH
2.7V
DATA RETENTION MODE
V
DR
2V
CE1
V
DR
- 0.2V
t
VR
Low VCC Data Retention Waveform (2) (CE2 Controlled)
VCC
CE2
t
CDR
V
IL
2.7V
t
R
V
IL
2.7V
DATA RETENTION MODE
V
DR
2V
t
VR
0.2V
CE2
LP62S2048-I Series
(August, 2001, Version 1.0)
13
AMIC Technology, Inc.
Ordering Information
Part No.
Access Time (ns)
Operating Current
Max. (mA)
Standby Current
Max. (
A)
Package
LP62S2048M-70LI
30
50
32L SOP
LP62S2048M-70LLI
30
10
32L SOP
LP62S2048V-70LI
30
50
32L TSOP
LP62S2048V-70LLI
70
30
10
32L TSOP
LP62S2048X-70LI
30
50
32L TSSOP
LP62S2048X-70LLI
30
10
32L TSSOP
LP62S2048U-70LI
30
50
36L CSP
LP62S2048U-70LLI
30
10
36L CSP
LP62S2048M-10LI
30
50
32L SOP
LP62S2048M-10LLI
30
10
32L SOP
LP62S2048V-10LI
30
50
32L TSOP
LP62S2048V-10LLI
100
30
10
32L TSOP
LP62S2048X-10LI
30
50
32L TSSOP
LP62S2048X-10LLI
30
10
32L TSSOP
LP62S2048U-10LI
30
50
36L CSP
LP62S2048U-10LLI
30
10
36L CSP
LP62S2048-I Series
(August, 2001, Version 1.0)
14
AMIC Technology, Inc.
Package Information
SOP (W.B.) 32L Outline Dimensions
unit: inches/mm
1
E
H
E
L
L
E
c
16
See Detail F
Detail F
17
32
e
1
e
1
A
1
A
2
A
s
D
Seating Plane
D y
e
b
~~
Symbol
Dimensions in inches
Dimensions in mm
A
0.118 Max.
3.00 Max.
A
1
0.004 Min.
0.10 Min.
A
2
0.1060.005
2.690.13
b
0.016 +0.004
0.41 +0.10
-0.002
-0.05
c
0.008 +0.004
0.20 +0.10
-0.002
-0.05
D
0.805 Typ. (0.820 Max.)
20.45 Typ. (20.83 Max.)
E
0.4450.010
11.300.25
e
0.050 0.006
1.270.15
e
1
0.525 NOM.
13.34 NOM.
H
E
0.5560.010
14.120.25
L
0.0310.008
0.790.20
L
E
0.0550.008
1.400.20
S
0.044 Max.
1.12 Max.
y
0.004 Max.
0.10 Max.
0
~ 10
0
~ 10
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
LP62S2048-I Series
(August, 2001, Version 1.0)
15
AMIC Technology, Inc.
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
e
L
E
L
GAUGE PLANE
A
A
2
c
0.25
BSC
Detail "A"
D y
Detail "A"
S
A
1
b
H
D
D
E
0.10(0.004)
M
12.0
Symbol
Dimensions in inches
Dimensions in mm
A
0.047 Max.
1.20 Max.
A
1
0.0040.002
0.100.05
A
2
0.0390.002
1.000.05
b
0.0080.001
0.200.03
c
0.0060.001
0.150.02
D
0.7240.004
18.400.10
E
0.3150.004
8.000.10
e
0.020 TYP.
0.50 TYP.
H
D
0.7870.007
20.000.20
L
0.0200.004
0.500.10
L
E
0.031 TYP.
0.80 TYP.
S
0.0167 TYP.
0.425 TYP.
Y
0.004 Max.
0.10 Max.
0
~ 6
0
~ 6
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
LP62S2048-I Series
(August, 2001, Version 1.0)
16
AMIC Technology, Inc.
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
e
Detail "A"
D
0.10MM
Detail "A"
S
b
D
1
E
D
L
E
L
GAUGE PLANE
A
A
2
c
0.25
BSC
Detail "A"
A
1
SEATING PLANE
12.0
Symbol
Dimensions in inches
Dimensions in mm
A
0.049 Max.
1.25 Max.
A
1
0.002 Min.
0.05 Min.
A
2
0.0390.002
1.000.05
b
0.0080.001
0.200.03
c
0.0060.0003
0.150.008
E
0.3150.004
8.000.10
e
0.020 TYP.
0.50 TYP.
D
0.5280.008
13.400.20
D
1
0.4650.004
11.800.10
L
0.020.008
0.500.20
L
E
0.0266 Min.
0.675 Min.
S
0.0109 TYP.
0.278 TYP.
y
0.004 Max.
0.10 Max.
0
~ 6
0
~ 6
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
LP62S2048-I Series
(August, 2001, Version 1.0)
17
AMIC Technology, Inc.
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
//
0.25
C
A
(0.36)
A
B
C
D
E
F
G
H
1 2 3 4 5 6
1
2
3
4
5
6
C
0.10
C
S
0.25
S
A B
b (36X)
BOTTOM VIEW
Ball*A1 CORNER
E
E
1
e
B
e
D
1
D
A
0.20(4X)
0.10
C
Dimensions in mm
Symbol
MIN.
NOM. MAX.
A
1.00
1.10
1.20
A
1
0.16
0.21
0.26
A
2
0.48
0.53
0.58
D
5.80
6.00
6.20
E
7.80
8.00
8.20
D
1
---
3.75
---
E
1
---
5.25
---
e
---
0.75
---
b
0.25
0.30
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
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