AS1150
,
AS1151
Quad LVDS Receivers
austria
micro
systems
D a ta S h e e t
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1 General Description
The AS1150 and AS1151 are quad flow-through LVDS
(low-voltage differential signaling) receivers which
accept LVDS differential inputs and convert them to
LVCMOS outputs. The receivers are perfect for low-
power low-noise applications requiring high signaling
rates and reduced EMI emissions.
The devices are guaranteed to receive data at speeds
up to 500Mbps (250MHz) over controlled impedance
media of approximately 100
. Supported transmission
media are PCB traces, backplanes, and cables.
The AS1150 uses high impedance inputs and requires
an external termination resistor when used in a point-to-
point connection. The AS1151 features integrated paral-
lel termination resistors (nominally 107
), which elimi-
nate the requirement for discrete termination resistors,
and reduce stub lengths.
The integrated failsafe feature sets the output high if the
inputs are open, undriven and terminated, or undriven
and shorted. Enable inputs (EN and ENn internally
pulled down to GND) control the high-impedance output
and are common to all four receivers. All inputs conform
to the ANSI TIA/EIA- 644 LVDS standards. Flow-through
pinout simplifies PC board layout and reduces crosstalk
by separating the LVDS inputs and LVCMOS outputs.
The devices are available in a 16-pin TSSOP package.
Figure 1. Block Diagrams
2 Key Features
!
Flow-Through Pinout
!
Guaranteed 500Mbps Data Rate
!
300ps Pulse Skew (Max)
!
Conform to ANSI TIA/EIA-644 LVDS Standards
!
Single +3.3V Supply
!
Operating Temperature Range: -40 to +85C
!
Failsafe Circuit
!
Integrated Termination (AS1151)
!
16-pin TSSOP Package
3 Applications
The devices are ideal for digital copiers, laser printers,
cellular phone base stations, add/drop muxes, digital
cross-connects, dslams, network switches/routers,
backplane interconnect, clock distribution computers,
intelligent instruments, controllers, critical microproces-
sors and microcontrollers, power monitoring, and porta-
ble/battery-powered equipment.
Rx
107
Rx
Rx
Rx
AS1151
AS1150
Rx
Rx
Rx
Rx
EN
ENn
IN4-
IN4+
IN3-
IN3+
IN2-
IN2+
IN1-
IN1+
OUT1
OUT2
OUT3
OUT4
EN
ENn
IN4-
IN4+
IN3-
IN3+
IN2-
IN2+
IN1-
IN1+
107
107
107
OUT1
OUT2
OUT3
OUT4
V
CC
V
CC
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AS1150, AS1151
austria
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Data Sheet
4 Absolute Maximum Ratings
Stresses beyond those listed in
Table 1
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in
Section 5 Electrical
Characteristics on page 3
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 1. Absolute Maximum Ratings
Parameter
Min
Max
Units
Notes
V
CC
to GND
-0.3
+5.0
V
INx+, INx- to GND
-0.3
+5.0
V
EN, ENn to GND
-0.3
V
CC
+ 0.3
V
OUTx to GND
-0.3
V
CC
+ 0.3
V
Continuous Power Dissipation
(T
AMB
= +70C)
750
mW
Derate 9.4mW/C Above +70C
Storage Temperature Range
-65
+150
C
Maximum Junction Temperature
+150
C
Operating Temperature Range
-40
+85
C
ESD Protection
-4
+4
kV
Human Body Model, INx+, INx-
Package Body Temperature
260
C
The reflow peak soldering
temperature (body temperature)
specified is in compliance with
IPC/JEDEC J-STD-020C
"Moisture/ Reflow Sensitivity
Classification for Non-Hermetic
Solid State Surface Mount
Devices".
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AS1150, AS1151
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Data Sheet
DC Electrical Characteristics
5 Electrical Characteristics
DC Electrical Characteristics
V
CC
= +3.0 to +3.6V, Differential Input Voltage |V
ID
| = 0.1 to 1.0V, Common-Mode Voltage V
CM
= |V
ID
/2| to
2.4V - |V
ID
/2|,T
AMB
= -40 to +85C. Typical values are at V
CC
= +3.3V, T
AMB
= +25C (unless otherwise specified).
1
Notes:
1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except V
TH
, V
TL
, and V
ID
.
2. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Table 2. DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LVDS Inputs (INx+, INx-)
Differential Input High
Threshold
V
TH
100
mV
Differential Input Low
Threshold
V
TL
-100
mV
Input Current (AS1150)
I
IN
x+,
I
IN
x-
0.1V
|V
ID
|
0.6V -20
20
A
0.6V
|V
ID
|
1.0V
-25
25
A
Power-Off Input Current
(AS1150)
I
INOFF
0.1V
|V
ID
|
0.6V, V
CC
= 0
-20
20
A
0.6V
|V
ID
|
1.0V, V
CC
= 0
-25
25
A
Input Resistor 1 (AS1150)
R
IN1
V
CC
= 3.6V or 0,
Figure 16 on page 9
1
35
k
Input Resistor 2 (AS1150)
R
IN2
V
CC
= 3.6V or 0,
Figure 16 on page 9
1
132 k
Common Mode Input
Resistance
R
INCM
AS1151: Input = 0
150
k
Differential Input
Resistance
R
DIFF
AS1151: V
CC
= 3.6V or 0,
Figure 16 on
page 9
90
107
132
LVCMOS/LVTTL Outputs (OUTx)
Output High Voltage
(
Table 5
)
V
OH
I
OH
= -4.0mA
(
AS1150
)
Open, undriven short, or
undriven 100
parallel
termination
2.7
3.2
V
V
ID
= +100mV
2.7
3.2
I
OH
= -4.0mA
(AS1151)
Open or Undriven Short
2.7
3.2
V
ID
= +100mV
2.7
3.2
Output Low Voltage
V
OL
I
OL
= +4.0mA, V
ID
= -100mV
0.1
0.25
V
Output Short-Circuit
Current
2
I
OS
Enabled, V
ID
= 0.1V, V
OUTx
= 0
15
160
mA
Output High-Impedance
Current
I
OZ
Disabled, V
OUTx
= 0 or V
CC
-10 10
A
Logic Inputs (EN, ENn)
Input High Voltage
V
IH
2.0
V
CC
V
Input Low Voltage
V
IL
0
0.8 V
Input Current
I
IN
V
INx
= V
CC
or 0
-15
15
A
Supply
Supply Current
I
CC
Enabled, Inputs Open
5
11
mA
average value, |V
ID
| = 200mV
8
15
Disabled Supply Current
I
CCZ
Disabled, Inputs Open
300
500
A
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AS1150, AS1151
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Data Sheet
AC Electrical Characteristics
AC Electrical Characteristics
V
CC
= +3.0 to +3.6V, C
LOAD
= 15pF, Differential Input Voltage |V
ID
| = 0.2 to 1.0V, Common-Mode Voltage V
CM
= |V
ID
/2|
to 2.4V -|V
ID
/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, T
AMB
= -40 to +85C. Typical
values are at V
CC
= +3.3V, V
CM
= 1.2V, |V
ID
| = 0.2V, T
AMB
= +25C (unless otherwise specified).
1, 2
Notes:
1. AC parameters are guaranteed by design and characterization.
2. C
L
includes scope probe and test jig capacitance.
3. t
SKD1
is the magnitude difference of differential propagation delays in a channel. t
SKD1
= |t
PHLD
- t
PLHD
|.
4. t
SKD2
is the magnitude difference of the t
PLHD
or t
PHLD
of one channel and the t
PLHD
or t
PHLD
of any other chan-
nel on the same device.
5. t
SKD3
is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same V
CC
and within 5C of each other.
6. t
SKD4
is the magnitude difference of any differential propagation delays between devices operating over rated
conditions.
7. f
MAX
generator output conditions:
a. Rise time = fall time = 1ns (0 to 100%)
b. 50% duty cycle
c. V
OH
= +1.3V
d. V
OL
= +1.1V
8. Output criteria:
a. Duty cycle = 60% to 40%
b. V
OL
= 0.4V (max)
c. V
OH
= 2.7V (min)
d. Load = 15pF
Table 3. AC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Differential Propagation Delay High-
to-Low
t
PHLD
Figure 18 on page 11
and
Figure 19 on
page 12
1.6 2.0
3.1
ns
Differential Propagation Delay Low-
to-High
t
PLHD
Figure 18 on page 11
and
Figure 19 on
page 12
1.6 2.0
3.1
ns
Differential Pulse Skew
(t
PHLD
- t
PLHD
)
3
t
SKD1
Figure 18 on page 11
and
Figure 19 on
page 12
140 300 ps
Differential Channel-to-Channel
Skew
4
t
SKD2
Figure 18 on page 11
and
Figure 19 on
page 12
400
ps
Differential Part-to-Part Skew
5
t
SKD3
Figure 18 on page 11
and
Figure 19 on
page 12
0.8 ns
Differential Part-to-Part Skew
6
t
SKD4
Figure 18 on page 11
and
Figure 19 on
page 12
1.5
ns
Rise Time
t
TLH
Figure 18 on page 11
and
Figure 19 on
page 12
0.5 1.0 ns
Fall Time
t
THL
Figure 18 on page 11
and
Figure 19 on
page 12
0.5 1.0
ns
Disable Time High-to-Z
t
PHZ
R
LOAD
= 2k
,
Figure 20 on page 12
and
Figure 21 on page 12
14 ns
Disable Time Low-to-Z
t
PLZ
R
LOAD
= 2k
,
Figure 20 on page 12
and
Figure 21 on page 12
14 ns
Enable Time Z-to-High
t
PZH
R
LOAD
= 2k
,
Figure 20 on page 12
and
Figure 21 on page 12
70 ns
Enable Time Z-to-Low
t
PZL
R
LOAD
= 2k
,
Figure 20 on page 12
and
Figure 21 on page 12
70 ns
Maximum Operating Frequency
7, 8
f
MAX
All Channels Switching
250
300
MHz
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AS1150, AS1151
austria
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Data Sheet
AC Electrical Characteristics
6 Typical Operating Characteristics
V
CC
= +3.3V, V
CM
= +1.2V, |V
ID
| = 0.2V, C
LOAD
= 15pF, T
AMB
= +25C, unless otherwise noted.
Figure 2. Supply Current vs. Frequency
Figure 3. Supply Current vs. Temperature
Figure 4. Diff. Threshold Voltage vs. V
CC
Figure 5. Output Short-Circuit Current vs. V
CC
Figure 6. Output Low Voltage vs. V
CC
Figure 7. Output High Voltage vs. V
CC
0
10
20
30
40
50
60
70
80
90
100
0,01
0,1
1
10
100
1000
Frequency (MHz)
S
uppl
y
Cur
r
ent
(
m
A
)
.
0
2
4
6
8
10
12
14
-40
-20
0
20
40
60
80
100
Temperature (C)
S
uppl
y
Cur
r
ent
(
m
A
)
.
All Channels Switching
One Channel Switching
Outputs Low
Outputs High
0
10
20
30
40
50
60
70
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
Di
f
f
.
T
h
r
e
s
hol
d V
o
lt
age
(
m
V
)
.
0
20
40
60
80
100
120
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
Ou
tp
u
t
S
h
o
r
t-
C
i
r
c
u
i
t C
u
r
r
e
n
t (
m
A
)
.
Low to High
High to Low
2,7
2,9
3,1
3,3
3,5
3,7
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
O
u
t
put
Hi
gh V
o
lt
age
(
V
)
.
105
106
107
108
109
110
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
O
u
t
p
ut
L
o
w V
o
lt
age (
m
V
)
.
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AS1150, AS1151
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Data Sheet
AC Electrical Characteristics
Figure 8. Differential Propagation Delay vs. V
CC
Figure 9. Differential Propagation Delay vs. Temperature
Figure 10. Differential Propagation Delay vs. V
CM
Figure 11. Differential Propagation Delay vs. V
ID
Figure 12. Differential Pulse Skew vs. V
CC
Figure 13. Transition Time vs. V
CC
2
2,04
2,08
2,12
2,16
2,2
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
Di
f
f
.
P
r
o
pagat
ion
Delay
(
n
s
)
.
t
PHLD
t
PLHD
2
2,05
2,1
2,15
2,2
2,25
-45
-25
-5
15
35
55
75
95
Tem perature (C)
Di
f
f
.
P
r
o
pagat
ion Delay
(
n
s
)
.
t
PHLD
t
PLHD
1,9
2
2,1
2,2
2,3
2,4
2,5
-0,5
0
0,5
1
1,5
2
2,5
Common-Mode Voltage (V)
D
i
ff. P
r
o
pagat
ion Delay
(
n
s
)
.
t
PHLD
t
PLHD
1,8
1,9
2
2,1
2,2
2,3
0,1
0,5
0,9
1,3
1,7
2,1
2,5
Differential Input Voltage (V)
D
i
ff. P
r
o
p
a
g
a
t
i
o
n
D
e
l
a
y
(
n
s
)
.
t
PHLD
t
PLHD
40
45
50
55
60
65
70
75
80
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
D
i
ff. P
u
l
s
e
S
k
e
w
(
p
s
)
.
300
320
340
360
380
400
3
3,1
3,2
3,3
3,4
3,5
3,6
Supply Voltage (V)
T
r
ans
it
ion T
i
m
e
(
p
s
)
.
t
TLH
t
THL
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AS1150, AS1151
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Data Sheet
AC Electrical Characteristics
Figure 14. Transition Time vs. Temperature
250
300
350
400
450
500
-45
-25
-5
15
35
55
75
95
Temperature (C)
T
r
ans
it
i
on T
i
m
e
(
p
s
)
.
t
TLH
t
THL
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AS1150, AS1151
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Data Sheet
Pin Assignments
7 Pinout
Pin Assignments
Figure 15. Pin Assignments (Top View)
Pin Descriptions
Table 4. Pin Descriptions
Pin Number
Pin Name
Description
1
IN1-
Inverting Differential Receiver Input
2
IN1+
Noninverting Differential Receiver Input
3
IN2+
Noninverting Differential Receiver Input
4
IN2-
Inverting Differential Receiver Input
5
IN3-
Inverting Differential Receiver Input
6
IN3+
Noninverting Differential Receiver Input
7
IN4+
Noninverting Differential Receiver Input
8
IN4-
Inverting Differential Receiver Input
9
ENn
Receiver Enable Input. Internally pulled down to GND.
When EN = high and ENn = low or open, the receiver outputs are active. For other
combinations of EN and ENn, the outputs are disabled and in high impedance.
10
OUT4
LVCMOS/LVTTL Receiver Output
11
OUT3
LVCMOS/LVTTL Receiver Output
12
GND
Ground
13
V
CC
Power-Supply Input. Bypass V
CC
to GND with 0.1F and 0.001F ceramic
capacitors.
14
OUT2
LVCMOS/LVTTL Receiver Output
15
OUT1
LVCMOS/LVTTL Receiver Output
16
EN
Receiver Enable Input. Internally pulled down to GND.
When EN = high and ENn = low or open, the receiver outputs are active. For other
combinations of EN and ENn, the outputs are disabled and in high impedance.
AS1150
AS1151
1
IN1-
2
IN1+
3
IN2+
4
IN2-
5
IN3-
6
IN3+
7
IN4+
8
IN4-
16 EN
15 OUT1
14 OUT2
13 V
CC
12 GND
11 OUT3
10 OUT4
9 ENn
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Data Sheet
LVDS Interface
8 Detailed Description
The AS1150 and AS1151 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-
power applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output.
The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V.
The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input
voltage range, a 1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground refer-
ences of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated.
LVDS Interface
The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-imped-
ance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower volt-
age swing than other common communication standards, resulting in higher data rates, reduced power consumption
and EMI emissions, and less susceptibility to noise.
The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground.
The AS1151 has an integrated termination resistors connected internally across each receiver input. This internal ter-
mination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In
other words, the transmission line is terminated on the IC.
Failsafe Circuit
The devices contain an integrated failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or
undriven and shorted.
Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are
high impedance. A short condition also can occur because of a cable failure. The failsafe circuit of the AS1150/AS1151
automatically sets the output high if any of these conditions are true.
The failsafe input circuit
(see Figure 16)
samples the input common-mode voltage and compares it to V
CC
- 0.3V (nom-
inal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than V
CC
-
0.3V and the failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel ter-
minated, there is no input current. In this case, a pullup resistor in the failsafe circuit pulls both inputs above V
CC
- 0.3V,
activating the failsafe circuit and thus forcing the device output high.
Figure 16. Failsafe Input Circuit
V
CC
- 0.3V
R
IN2
R
IN1
R
IN1
R
DIFF
AS1151
V
CC
- 0.3V
R
IN2
R
IN1
R
IN1
AS1150
INx-
OUTx
INx+
INx-
OUTx
INx+
V
CC
V
CC
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Data Sheet
9 Applications
Figure 17. Typical Application Circuit
Power-Supply Bypassing
To bypass V
CC
, use high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the
device as possible, with the smaller valued capacitor closest to pin V
CC
.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1150 and AS1151.
!
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor
must also be matched to this characteristic impedance.
!
Eliminate reflections and ensure that noise couples as common mode by running differential traces close together.
!
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper
data recovery of the devices.
!
Route each channel's differential signals very close to each other for optimal cancellation of their respective exter-
nal magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential
impedance.
!
Avoid 90 turns (use two 45 turns).
!
Minimize the number of vias to further prevent impedance irregularities.
Table 5. Function Table
Enable Pins
Input
Output
EN
ENn
INx+
INx-
OUTx
H
L or Open
V
ID
+100mV
H
V
ID
+100mV
L
AS1150 Open, undriven short, or undriven
100
parallel termination
H
AS1151 Open or undriven short
Other Combinations of Enable Pin Settings
Don't Care
Z
LVDS
Signals
107
107
107
107
LVTTL/LVC-
MOS
Data Inputs
LVTTL/LVC-
MOS
Data Outputs
100
Shielded Twisted Cable or Microstrip PC Board Traces
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
AS1151
AS1152
Quad LVDS Driver
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Data Sheet
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
!
Use cables and connectors with matched differential impedance (typically 100
) to minimize impedance mis-
matches.
!
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
!
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
!
The AS1151 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in
Table 2 on page 3
.
!
The AS1150 requires an external termination resistor. The termination resistor should match the differential imped-
ance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance val-
ues may range between 90 to 132
depending on the characteristic impedance of the transmission medium. Use
1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
!
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
!
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
!
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
!
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Propagation Delay and Transition Time Test Circuit
INx+
50
50
INx-
OUT
C
L
Pulse
Generator**
* 50
required for pulse generator.
** When testing the AS1151, adjust the pulse generator output
to account for internal termination resistor.
Receiver Enabled
1/4 AS1150, AS1151
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Revision 1.19
12 - 15
AS1150, AS1151
austria
micro
systems
Data Sheet
Figure 19. Propagation Delay and Transition Time Waveforms
Figure 20. High Impedance Delay Test Circuit
Figure 21. High Impedance Delay Waveforms
INx+
INx-
V
OL
OUTx
V
OH
V
ID
V
ID
= 0
t
THL
t
TLH
t
PLHD
t
PHLD
V
ID
= 0
80
50%
20
V
ID
= (V
IN
x
+
) - (V
IN
x
-
)
Note: V
CM
= (V
IN-
+ V
IN+
)
2
80
50%
20
OUTx
V
CC
Generator
50
INx-
C
L
R
L
INx+
Device
Under
Test
S1
ENn
EN
C
L
includes load and test JIG capacitance.
S
1 =
V
CC
for t
PZL
and
t
PLZ
measurements.
S
1 =
GND
for t
PZH
and
t
PHZ
measurements.
1.5V
EN when ENn = GND or Open
ENn when EN = V
CC
1.5V
1.5V
1.5V
0.5V
50%
50%
3V
0
V
CC
V
OL
V
OH
GND
t
PZL
t
PZH
t
PHZ
t
PLZ
0.5V
Output when
V
ID
= -100mV
Output when
V
ID
= +100mV
0
3V
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Revision 1.19
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AS1150, AS1151
austria
micro
systems
Data Sheet
Board Layout
10 Package Drawings and Markings
Figure 22. 16-Pin TSSOP Package
Notes:
1. All dimensions are in millimeters; angles in degrees.
2. Dimensions and tolerancing per ASME Y14.5M-1994.
3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15mm per side.
4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm
per side.
5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of
dimension b at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm for 0.5mm pitch packages.
6. Terminal numbers shown are for reference only.
7. Datums A and B to be determined at datum plane H.
8. Dimensions D and E1 to be determined at datum plane H.
9. This dimension applies only to variations with an even number of leads per side. For variations with an odd number
of leads per package, the center lead must be coincident with the package centerline, datum A.
10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
Symbol
0.65mm Lead Pitch
1, 2
Note
Symbol
0.65mm Lead Pitch
1, 2
Note
Min
Nom
Max
Min
Nom
Max
A
-
-
1.10
1
0
-
8
A1
0.05
-
0.15
L1
1.0 Ref
A2
0.85
0.90
0.95
aaa
0.10
L
0.50
0.60
0.75
bbb
0.10
R
0.09
-
-
ccc
0.05
R1
0.09
-
-
ddd
0.20
b
0.19
-
0.30
5
e
0.65 BSC
b1
0.19
0.22
0.25
2
12 Ref
c
0.09
-
0.20
3
12 Ref
c1
0.09
-
0.16
Variations
D
4.90
5.00
5.10
3, 8
e
0.65 BSC
E1
4.30
4.40
4.50
4, 8
N
16
6
E
6.4 BSC
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Revision 1.19
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AS1150, AS1151
austria
micro
systems
Data Sheet
Board Layout
11 Ordering Information
Model
Description
Package Type
Delivery Form
AS1150
Quad low-voltage differential signaling receiver
16-pin TSSOP
Tubes
AS1150-T
Quad low-voltage differential signaling receiver
16-pin TSSOP
Tape and Reel
AS1151
Quad low-voltage differential signaling receiver with
integrated termination
16-pin TSSOP
Tubes
AS1151-T
Quad low-voltage differential signaling receiver with
integrated termination
16-pin TSSOP
Tape and Reel
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Revision 1.19
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AS1150, AS1151
austria
micro
systems
Data Sheet
Board Layout
Copyrights
Copyright 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered . All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami-
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-
sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-
nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com
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micro
systems
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