ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 2 of 14

Austria Mikro Systeme International AG

K e y F e a t u r e s

Supports triple band operation: Europe 868 MHz and 433 MHz-, US and Japan 315 MHz ISM

band.

Designed to be conform to EN 300 220, and FCC 47 CFR Ch.1 par.15 requirements.

Provides highly reliable packet oriented data transmission in blocks of 128 bit.

Event oriented single message transmission and status oriented and continuous message

transmission supported.

Special transmission protocol for high reliability even in presence of burst interferer (e.g.

GSM) implemented.

RX sensitivity of the receiver typical -100 dBm.

Supports clock for an external µC and allows clock free total shut down of the whole system.

Wide supply range between 2.7 to 5.5 V.

Low RX current, typical 10 mA @ 2.4 V.

Low idle mode current, typical 1.2mA.

Wide operating temperature range from 40 °C to +85 °C.

Only a low cost XTAL for 25 ppm (868 MHz) or 50 ppm (433 and 315 MHz) reference fre-

quency tolerance required.

Minimum only 1 XTAL and 4 capacitors externally required.

G e n e r a l D e s c r i p t i o n

The ASCell3912 is a low power, triple ISM band (868 / 433 / 315 MHz), single channel FSK re-
ceiver designed to work in a remote control link together with the SC3911 transmitter system
cell.

The ASCell3912 performs packet oriented data transmission, in a single message- or continuos-
message mode using a special protocol to ensure high reliability even in presence of strong
pulsed interferers in close adjacent bands like e.g. GSM.

A general bi-directional micro-controller (µC) interface is provided, to support the µC with clock-
and reset- signal, and to operate the highly efficient power up/down management.

As external components the SC3911 need at minimum only a reference XTAL, and 4 capacitors.

A p p l i c a t i o n s

Key-less car entry systems.

Short range packet oriented data transmission.

Security applications and alarm systems.

Domestic remote control systems.

Industrial remote control systems.

Remote metering.

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 3 of 14

Austria Mikro Systeme International AG

TSSOP-20

D_EN

WAKEUP

RE_INT

µC_CLK

TEST2

TEST1

DGND

D_CLK

DATA

DVDD

RF+

RF-

LC+

LC-

XTAL+

XTAL-

AVDD

AGND

GMC

RFGND

This pin-out is preliminary and will change for the real implementation!

This document contains information on products under development. Austria Mikro Systeme International AG reserves the right to
change or discontinue this product without notice.

F u n c t i o n a l D e s c r i p t i o n

The Figure 1 shows the block diagram of the ASCell3912. The analog part of the ASCell3912
consists of a direct conversion receiver, a triple band RF synthesizer and the DC-cancellation.
The digital part includes the burst interference resistant protocol decoder the control logic and
the µC interface.

Digital
Power

Supply

XO-SEL

LC
+

LC
-

M
C

TE
ST
2

D_
CL

D_
E

DA
TA

VDD

GND

AGND

RF-

AVDD

XTAL+

RF+

XTAL-

DC-Offset

Bandwith

90°

DATA-

RECOVERY

10dB

OSC

PLL

-Det

DEM

CTRL

AFC

SYNC

FIR

CLK

GEN

SETUP-

INTERFACE

RF-Power

Power

Supply

PROTOCOL

DECODER

Scan

Test

XOT[3:0]

XO-CLK

RF-SEL

STATE REGISTER

Functional

Test

1/STR

µC

_C
LK

_I
NT

W
AK

E_
UP

LNA

RFGND

TEST1

Sleeptime

control

Figure 1:

Block diagram of the ASCell3912.

ASCell3912

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 4 of 14

Austria Mikro Systeme International AG

1.1 Analog Receiver Part

The input signal is a low to moderately high modulation index continuous phase frequency shift
keying modulated RF signal around a carrier Fc. This signal is amplified by the low noise ampli-
fier (LNA) and fed to the In-phase and Quadrature-phase mixers (I/Q mixers). The mixers con-
vert the RF signal directly to base band. The local oscillator signal for the I/Q mixers is generated
by the on-chip PLL.

The two base band signals (signals I and Q) are filtered and further amplified. After DC offset
cancellation to remove the static and quasi-static DC offsets and to ensure fast wake-up of the
receiver, the signals are hard limited. The rectangular signals I' and Q' are fed to the digital part
where demodulation and the further signal processing is applied.

1.1.1 RF Synthesizer

Frequency synthesis is performed by a conventional synthesizer consisting of a phase detector,
a charge pump, a voltage controlled oscillator working at 315~868.3 MHz, and a feedback divider
by 16 (315.00MHz); 32 (315, 433.92MHz), or 64 (868.3MHz). A truth table for the different fre-
quencies is given in Table 1.

XOSC

/ MHz Multiplier

/ MHz

FB1

FB0

RF-SEL XO-SEL

19,6875

315.000

13.5600

433.920

13.5672

868.300

Table 1:

Quartz and RF output frequencies.

Note: XO-SEL and RF-SEL are intenal generated Signals from the FB[1:0] bits of the setup information.

1.1.2 LNA

The amplification of the LNA can be switched in two states. The gain can be switched of about
10dB with the LNA bit of the setup command.

Note: LNA is one bit of the setup information.

1.1.3 I/Q Down Converter

The ASCell3912 contains a high performance quadrature down converter with low DC offset and
high isolation of RF- and LO-ports.

1.1.4 Base Band Filter

To achieve optimum blocking performance, the base band filter is realized in two separated cir-
cuit blocks. The first filter block removes high level blocking signals out of receive band, the sec-
ond filter block serves for high selectivity of adjacent interferers.

1.1.5 DC-Cancellation and Adjustment of Lower Cut-Off Frequency

The DC offset is removed by a first order high-pass with switchable limit frequency. In the first
step the frequency offset of transmitter and receiver is not compensated, therefore the lower
band limit is about 10 kHz. In the second step, the receiver frequency is adjusted and the lower
limit frequency of the DC-block is set to about 40 kHz and therefore the total bandwidth of pass
band is reduced. At the output of the DC block is a switch to initialize the DC-offset in the power-
up instant, at the instant of switching, and after appearance of high level interfering signals.

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 5 of 14

Austria Mikro Systeme International AG

1.2 Digital Controller

The principal function of the digital controller is demodulation, bit synchronization and the detec-
tion of the received data protocol, according to the definition of transmitted bits. Furthermore, a
first syntax check and plausibility check of detected data is provided. A data protocol received
completely is put into a receive buffer, where a micro controller (µC) can read it out via a serial
interface.

The receiver can be externally configured with several operation parameters, LNA gain setting,
used frequency band, and timing constant for the watch dog timer. The serial interface also al-
lows to configure the digital controller by the µC.

The receiver writes the state information into a status register. This status information can be
read out from the µC out of the status register of the receiver.

1.2.1 Microprocessor Clock

The microprocessor clock frequency F

CLK

is generated by dividing the XTAL frequency F

XOSC

4 if XO-SEL is ´H´ and by dividing the XTAL frequency F

XOSC

by 6 if XO-SEL is ´L´.

Note: XO-SEL and RF-SEL are internal generated signals from the FB[1:0] bits of the setup information.

1.2.2 ASCell3912 Digital Part Timing

In Figure 2 the timing of a complete receive sequence can be seen. Transmission starts at an
arbitrary point in time. First the crystal oscillator is switched on. A minimum time of 5 ms is al-
lowed for the frequency to settle to the final value. Then the receiver executes a wake-up se-
quence consisting of 6 wake-up bursts. The wake-up bursts are unequally spaced to guarantee
interference free detection of an ongoing transmission also in the presence of burst interferers.
During a wake-up burst the receiver scans for an active transmission on the air interface. The
wake-up sequence is optimized to combat GSM and CT2 type interferers.

After an ongoing transmission has been detected the receiver goes to receiving mode, the
WAKE_UP line goes high, and reception of data starts. Depending on the number of interferers
present, reception of all data may take up to 3 data blocks. As soon as all data has been de-
tected successfully, the RE_INT pin issues a positive pulse, to indicate the availability of data,
and the internal data ready flag (DR) in the ASCell3912 state register is set. The RE_INT line
may be used to trigger a interrupt procedure, which is executed at the availability of data. When
data is read out by the micro controller the internal data ready flag (DR) in the RX-status register
is cleared and it is only set, when a complete data sequence has received again. No further
pulse is issued on the RE_INT line, but the micro controller has to poll for new data during an
ongoing reception. If transmission stops, the WAKE_UP line goes low and a pulse is issued on
the RE_INT line to indicate the termination of transmission at CMT.

In Figure 2 also the timing where the microprocessor clock (µC_CLK) is active is shown. The
clock is active with the start of the detection phase of the SC3911. The clock is shut down 16
clock cycles (T

CAI

) after the falling edge of the second interrupt on the RE_INT pin.

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 6 of 14

Austria Mikro Systeme International AG

µC-readout

WAKE_UP

Receiver-sleep-time =

(STR +1) * 20 ms

SYNC

13.80ms

DATA

12.28ms

SYNC

13.80ms

DATA

12.28ms

SYNC

13.80ms

DATA

12.28ms

SYNC

13.80ms

DATA

12.28ms

Receiver Wake up sequence

max. 22.25ms

XO-

Set

DET1

=26.08ms

XOS

=5ms

Wake-Up

trigger

Wake up

start

detection

TX-Start

Wake-Up

trigger

TX- stop

RX-sleep

INT

= 0.5ms

Data reception and store data

XO-
Set

SYNC

13.80m

DATA

Data reception

RX-
Status

TX-

Status

data detection

completed

shown for T

DET1

STOP

30ms

RE_INT

BWI

0.5ms

Interface-lines: Shown for T

DET1

Internal flags:

Shown for T

DET1

DET0

=12.28ms

DET2

=64.44ms

Detection with 0 GSM-interferer

DET0

=12.28ms

Detection with 1 GSM interferer or in 50% Duty Cycle ModeT

DET1

=26.08ms

Detection with 2 GSM interferer

DET2

=64.44ms

Active time after last useful data

STOP

30ms

Cristal Oscillator setup-time

XOS

=5ms

µC_CLK

CAI

= 16/F

CLK

Figure 2:

ASCell3912 basic timing.

Note: The Interface timing and the timing of the internal flags are shown in Figure 2 for a detection time of T

DET1

1.2.3 Receiver Configuration

The configuration register can be loaded from a µC via the serial interface. The Table 2 below
shows the contents of the configuration register. Bit b0 is the first transmitted bit. The setup
contains the LNA set, frequency band and the sleep time interval of the receiver.

bit #

Name

Description

Configuration

Comments

LNA

LNA gain switch

L= LNA Gain is high
H= LNA Gain is -10dB

default

[1..2]

FB[1:0]

Frequency band select with
FB1 is MSB

L, L (FB1, FB0) = 868.3 MHz
L, H = 433.92 MHz
H, L = 315 MHz
H, H = not used

default

[3..8]

STR[5:0]

Sleep time interval set of
the receiver, with STR5 is
MSB

sleep

= (STR + 1) * 20ms

Note: for STR = 00h the
witing period between
two consecutive wake-
up cycles will be 148 bit.

Table 2: Format of the configuration Register

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 7 of 14

Austria Mikro Systeme International AG

1.2.4 Receiver Status

Table 3 below shows the format of the state register. Bit b0 is the first which is transmitted by a
readout of the µC. The status register contains the information about a successful received date,
active receiver and the information about the quality of the received signal.

bit #

Name

Description

Status

Comments

Data received a complete
message was received

L= no data received
H= data received successfully

Receiver is active

L= receiver not active
H= data reception in progress

Note: This bit is set by the
receiver when 6 bytes of a
packet are correct. This bit in
the status register is neces-
sary for the comfort-orientated
functions of the central locking
functions.

[2..3]

RQ[1:0]

Signal quality indicates
how many data packets
are necessary for a com-
plete message

L, L (RQ1, RQ0) = 1 packet
L, H = 2 packets
H, L = 3 packets
H, H =4 packets

Table 3:

Format of the status register.

1.2.5 µC Interface

The ASCell3912 contains a direct interface to a micro controller (µC). The µC interface of the
ASCell3912 consist of the following five pins:

"Transmit/Received data input/output" (DATA). A bi-directional serial data line, with states "H"
(recessive, or weak pull-up) and "L" (dominant).

"Active "H" transmit data enable" (D_EN)

"Transmit data clock input" (D_CLK).

"Active "H" µC interrupt output " (RE_INT).

"Active "H" µC wakeup output " (µC_WAKEUP).

"µC clock output " (µC_CLK).

1.2.5.1

Instruction Set

The following table shows the instruction set of the interface. The first two bits are the operation
code, which determine the direction of the data transfer and which data is transferred.

Operation

code

Instruction or Data

Comment

LNA

FB1

FB0

STR5

STR4

STR3

STR2

STR1

STR0

Write ASCell3912 setup

LNA

FB1

FB0

STR5

STR4

STR3

STR2

STR1

STR0

Read ASCell3912 setup

RQ1

RQ0

Read ASCell3912-State

B0-b0

B15-b7

Read ASCell3912-Data

Table 4:

Overview of the instruction set.

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 8 of 14

Austria Mikro Systeme International AG

1.2.6 Timing Diagrams

The following Figure 3 shows the timing for the write operation into the configuration register.
First the opcode is transmitted and it is followed by 9 instruction bits.

FB1

LNA

STR0

D_CLK

DATA

D_EN

STR5

FB0

Figure 3:

Write timing for the configuration register..

The following Figure 4 shows the timing of a read operation from the status register. After writing
the operation code to the ASCell3912, the ASCell3912 stays in high impedance state for one
more clock cycle and starts transmission of the selected bit sequence after that period.

R X

RQ1

RQ0

D_CLK

DATA

D_EN

gap=1

µC

SC3912

Figure 4:

Read timing for status register.

In the following Figure 5 shows read out of the received data. In the example `Bx-bz` stands for
bit ´z´ of Byte ´y´, so B7-b5 depicts bit 5 of byte 7.

B15-b6

B15-b7

B0-b1

D_CLK

DATA

D_EN

gap=1

B0-b0

µC

SC3912

Figure 5:

Read out timing for received data (16 Bytes).

1.2.7 Interrupt and Wake-Up Pins

To provide the micro controller with time-critical information the receive/end transmission inter-
rupt (RE_INT) line is used. Figure 2 shows the timing of the RE_INT and WAKE_UP signals
during the reception. A high pulse is issued on this line, when one of the both conditions appear:

The reception of data is completed for the first time after a receiver wake-up.

The transmission of data has stopped. This interrupt is necessary status oriented CMT for

comfort orientated central locking functions (like window closing).

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 9 of 14

Austria Mikro Systeme International AG

To distinguish between the two interrupt sources, the WAKE_UP line is used, as listed in the
following table.

RE_INT

WAKE_UP Interrupt source

Message received completely

Transmission stopped

Table 5:

Interrupt sources and their meaning.

E l e c t r i c a l C h a r a c t e r i s t i c s

Absolute Maximum Ratings (non operating)

Symbol

Parameter

Min

Max

Units

Note

VDD; AVDD

Positive supply voltage

-0.5

GND; AGND

Negative supply voltage

Vin

Voltage at every input pin

Gnd-0.5

VCC+0.5

Iin

Input current into any pin except supply pins

-10

ESD

Electrostatic discharge

1) 3)

Tstg

Storage temperature

-55

125

°C

Tlead

Lead temperature

260

°C

1) Test according to MIL STD 883C, Method 3015.7: HBM: R=1.5 k

, C=100 pF, 5 positive pulses per pin against supply pins, 5

negative pulses per pin against supply pins [C2].

2) 260 °C for 10 sec (Reflow and Wave Soldering), 360 °C for 3 sec (Manual soldering).
3) All pins, pins XTAL+,XTAL-, RF+,RF-,LC+ and LC- have 500 V ESD protection

Operating Conditions

Symbol

Parameter

Conditions / Notes

Min

Typ

Max

Units

VDD=AVDD Positive supply voltage

2.7

5.5

GND=AGND Negative supply voltage

Operating temperature

-40

+85

°C.

run

Supply current into VDDA
and VDDD pin

Everything on

idle

Average supply current in
idle mode.

1.2

sleep

Average supply current in
sleep mode.

0,5

µA

in,max

Maximum input power level Above this level cir-

cuit could be de-
stroyed

dBm

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 10 of 14

Austria Mikro Systeme International AG

2.3 Receiver Operation

TA = 23 °C, VDD, AVDD = 3.6 V, unless specified otherwise. Devive functional for TA= -40 to
+85 °C.

Symbol

Parameter

Conditions / Notes

Min

Typ

Max

Units

Carrier Frequency

Depends on different external
crystals.

315.000
433.920
868.300

MHz
MHz
MHz

Input impedance

Capacitive part t.b.d.

200~ 400

? F

Nominal FSK frequency devi a-
tion

315, 433.92, 868.3MHz

kHz

xosc

Crystal oscillator (XOSC) fre-
quency

315,000 MHz: max +/- 50ppm
433.920 MHz: max +/- 50ppm
868.300 MHz: max +/-25ppm

19,6875
13.5600
13.5672

MHz
MHz
MHz

xosc

Crystal oscillator (XOSC) fre-
quency tolerance

315,000 MHz: (-40~+85 °C),
433.920 MHz: (-40~+85 °C),
868.300 MHz: (-40~+85 °C).

50
50
25

ppm
ppm
ppm

R,gross

Gross Data Rate

Including protocol.

18.235

kbps

Sens

Receiver sensitivity

-10 °C<TA<+70 °C

-96

-100

dBm

SensT

Temperature sensitivity reduc-
tion

-40<TA<-10 °C. or
+70>TA>+85 °C.

Sens

offim

Receiver sensitivity reduction
caused by frequency offset

@maximum receiver sensitiv-
ity reduction @ 44 kHz offset

SensLNA

Sensitivity reduction caused
by LNA gain switching

200KHz

Blocking immunity
200 kHz 1 MHz

Without external filter.

1MHz

Blocking immunity
1-10 MHz

Without external filter

10MHz

Blocking immunity @
>10 MHz

Without external filter

LOfeed

LO @ F

power available at

LC+ and LC- nodes

-28

dBm

Standard Receive Quality (SRQ): Message reception successfully finished after <80 ms in 80% of all transmission
trails.

CW blocking signal relative to applied useful signal with 94dBm power level and SRQ.
Measured without frequency offset and at +25 °C

Receiver Timing

Symbol

Parameter

Conditions / Notes

Min

Typ

Max

Units

Dni

Time to received FSK data

Configured for fast response
(receiver sleep time = 0)

Dwi

Time to received FSK data

Using low idle duty cycle the
(receiver sleep time >0)

stop

RX switch off time

Timeout for comfort functions

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 11 of 14

Austria Mikro Systeme International AG

2.5 Digital Pin Characteristics

AMB

= 23 °C, VDD = 3.6 V, unless specified otherwise. GND is the 0 V reference.

Symbol Parameter

Conditions

Min

Typ

Max

Units

µC_CLK (µC clock output)

VOH

High level output voltage

IOH =-1 mA

VDD-0.5

VOL

Low level output voltage

IOL =1 mA

0.3

Rise time

CLoad = 10 pF

Fall time

CLoad = 10 pF

jcc

Cycle to cycle jitter

+/-5

DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)

VIH

High level input voltage

VDD-0.5

VIL

Low level input voltage

0.3

IIH

High level input current

VIH= VDD

µA

IIL

Low level input current

VIL =0 V

-1

µA

D_CLK

D_CLK frequency

kHz

RE_INT (interrupt output); WAKEUP (µC wakeup output)

VOH

High level output voltage

IOH = -1mA

VDD-0.5

VOL

Low level output voltage

IOL = 1mA

0.3

P i n - o u t I n f o r m a t i o n

Note: pin numbers have arbitrary ordering and numbering - will be defined during design

Name

Type

Description

RF+

LNA input

RF-

LNA input

LC+

I/O

LNA tank

LC-

I/O

LNA tank

XTAL+

XTAL oscillator input

XTAL-

XTAL oscillator output

AVDD

Analog positive supply

AGND

Analog negative supply

GMC

I/O

Base-Band Low Pass frequency set

RFGND

RF GND

DGND

Digital negative supply

TEST1

I/O

pin for test purposes

TEST2

I/O

pin for test purposes

uC_CLK

Clock output for micro controller

RE_INT

Interrupt at first received data block and receive end

WAKEUP

Micro controller wake up; high during ongoing reception

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 12 of 14

Austria Mikro Systeme International AG

Name

Type

Description

D_EN

Enable data bus

D_CLK

Clock for serial interface

DATA

I/O

Data Input / Output for serial interface

DVDD

Digital positive supply

A p p l i c a t i o n S c h e m a t i c

DC to 100 kHz

RF_LO = f

R F

G. Schultes, ISM868_RX

Revision: 0, 99 07 16

f/64

+/-45°

Protocol

Decoder

Receiver

Timing

0°

90°

Baseband

Amplifiers

Compe-

rators

Switchable

AC-Coupling

Baseband

Filters

Demodulator,

Synchronizer

Sync

Data

Loop-filter

Divider

XTAL+

XTAL-

Phase Detector

XTAL

Oscillator

Local

Oscillator

Quadrature

Down Converter

RE_INT

DATA

D_EN
D_CLK

WAKEUP

µC_CLK

DVCC

DGND

TEST

f =868.300 MHz

R F

Pre Filter

IRF

QDC

2*BBF

2*BBA

2*CMP

XTO

VCO

LPF

DIV PHD

2*ACC

DEM

AFC

LNA

DC-0

Bandwidth

Clock

AGND

AGND

AVDD

AVDD

LC-

GMC

Preamp.

PRA

RFGND

RF+

LC+

RF-

DVCC

DGND

Implementation

Example

Optional

Figure 6: Basic application schematic of the ASCell3912.

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell Preliminary Data Sheet
ASCell3912

Rev. A, February 2000

Page 13 of 14

Austria Mikro Systeme International AG

P a c k a g e I n f o r m a t i o n

Figure 7: Physical dimensions of TSSOP-20.

Symbol

Common Dimensions

Minimal (mm/mil)

Nominal (mm/mil)

Maximal (mm/mil)

1.10/0.0433

0.05/0.002

0.10/0.004

0.15/0.006

0.19/0.0075

0.30/0.0118

0.65 BSC

6.25/0.246

6.40/0.252

6.50/0.256

4.30/0.169

4.40/0.173

4.50/0.177

0.50/0.020

0.60/0.024

0.70/0.028

0°

4°

8°

ASCell's are functional and in-spec circuits, which are usually available as samples with documentation and demoboard. How -
ever they are intentionally to be used as a basis for ASIC derivatives. If an ASCell fits into a customer's application as it is, it will
be immediately qualified and transfered to an ASSP to be ordered as a regular AS product.

2000, Austria Mikro Systeme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.

Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@amsint.com

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