2048-bits Serial Electrically Erasable PROM
AM93LC56
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/10
ATC
Features
State-of-the-art architecture
- Non-volatile data storage
- Standard voltage and low voltage operation
Vcc: 2.7V ~ 5.5V
- Full TTL compatible inputs and outputs
- Auto increment read for efficient data dump
Hardware and software write protection
- Defaults to write-disabled state at power up
- Software instructions for write-enable/disable
- VCC level verification before self-timed
programming cycle
Advanced low voltage CMOS EEPROM
technology
Versatile, easy-to-use interface
- Self-timed programming cycle
- Automatic erase-before-write
- Programming status indicator
- Word and chip erasable
- Stop SK anytime for power savings
Durability and reliability
- 40 years data retention
- Minimum of 1M write cycles per word
- Unlimited read cycles
- ESD protection
Connection Diagram
1
2
3
4
8
7
6
5
VCC
GND
NC
ORG
CS
SK
PDIP-8L / SOP-8L
DO
DI
1
2
3
4
8
7
6
5
VCC
GND
NC
ORG
CS
SK
Rotated SOP-8L
DO
DI
General Description
The AM93LC56 is the 2048-bit non-volatile serial
EEPROM. It is manufactured by using ATC's
advanced CMOS EEPROM technology. The
AM93LC56 provides efficient non-volatile read/write
memory arranged as 128 words of 16 bits each
when the ORG Pin is connected to VCC and 256
words of 8 bits each when it is tied to ground. The
instruction set includes read, write, and write
enable/disable functions. The data out pin (DO)
indicates the status of the device during the
self-timed non-volatile programming cycle.
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the WRITE ENABLE state and proper VCC
operation range is the WRITE instruction accepted
and thus to protect against inadvertent writes. Data
is written in 16 bits per write instruction into the
selected register. If Chip Select (CS) is brought
HIGH after initiation of the write cycle, the Data
Output (DO) pin will indicate the READY/BUSY
status of the chip.
The AM93LC56 is available in space-saving 8-lead
PDIP, 8-lead SOP and rotated 8-lead SOP package.
Pin Assignments
Name
Description
CS Chip
Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND Ground
VCC Power
Supply
NC No
Connection
ORG Internal
Organization
Ordering Information
Type
Package
56: 2K
S : SOP-8L
GS8: SOP-8L,G type
N : PDIP-8L
Temp. grade
AM 93 L C 56 X XX X
Packing
Blank :
C
o
70
~
C
o
0
+
I :
C
o
85
~
C
o
40
+
-
V :
C
o
125
~
C
o
40
+
-
Blank : Tube
A : Taping
Operating Voltage
LC : 2.7~5.5V,CMOS
2048-bits Serial Electrically Erasable PROM
AM93LC56
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
2/10
ATC
Block Diagrams
INSTRUCTION
REGISTER
(10 BITS)
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
DATA
REGISTER
ADDRESS
REGISTER
V
CC
RANGE
DETECTOR
WRITE ENABLE
DUMMY BIT
R/W AMPS
DECODER
HIGH VOLTAGE
GENERATOR
EEPROM
ARRAY
(128 X 16)
OR
(256 X 8)
DI
CS
SK
DO
ORG
Absolute Maximum Ratings
Characteristics
Symbol
Values
Unit
Storage Temperature
T
S
-65 to + 125
C
Voltage with Respect to Ground
-0.3
to +
6.5 V
NOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias
Values
Unit
AM93LC56
0 to + 70
C
AM93LC56I
-40 to + 85
C
AM93LC56V
-40 to +125
C
DC Electrical Characteristics
(Vcc =2.7~5.5V, Ta = 25
o
C , unless otherwise noted)
Parameter
Symbol
Conditions
Min
Max
Units
Operating current**
I
CC
CS=V
IH
, SK=1MHz CMOS input levels
3
mA
Standby current
I
SB
CS=DI=SK=0V
10 A
Input leakage
I
IL
V
IN
= 0V to V
CC(CS,SK,DI)
-1
1
A
Output leakage
I
OL
V
OUT
= 0V to V
CC
, CS=0V
-1
1
A
V
CC
= 3V + 10%
-0.1
0.15 V
CC
Input low voltage**
V
IL
V
CC
= 5V + 10%
-0.1
0.8
V
V
CC
= 3V + 10%
0.8 V
CC
V
CC
+0.2
Input high voltage**
V
IH
V
CC
= 5V + 10%
2
V
CC
+0.2
V
Output low voltage
V
OL1
I
OL
= 2.1mA TTL, V
CC
=5V + 10%
0.4
V
Output high voltage
V
OH1
I
OH
= -400uA TTL, V
CC
=5V + 10%
2.4
V
Output low voltage
I
OL
= 10uA CMOS
0.2
V
Output high voltage
V
OL2
I
OH
= -10uA CMOS
V
CC
-0.2 V
Note **: I
CC
, V
IL
min and V
IH
max are for reference only and are not tested
2048-bits Serial Electrically Erasable PROM
AM93LC56
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
3/10
ATC
AC Electrical Characteristics
(Vcc = 2.7V ~ 5.5V, Ta = 25
o
C , unless otherwise noted)
AM93LC56
Parameter
Symbol
Conditions
Min
Max
Units
SK Clock Frequency
F
SK
0 1
MHz
SK High Time
T
SKH
250
ns
SK Low Time
T
SKL
250
ns
Minimum CS Low Time
T
CS
250
ns
CS Setup Time
T
CSS
Relative to SK
50
ns
DI Setup Time
T
DIS
Relative to SK
100
ns
CS Hold Time
T
cSH
Relative to SK
0
ns
DI Hold Time
T
DIH
Relative to SK
100
ns
Output Delay to "1"
T
pD1
AC
Test
500
ns
Output Delay to "0"
T
pD0
AC
Test
500
ns
CS to Status Valid
T
SV
AC Test CL = 100pF
500
ns
CS to DO in 3-state
T
dF
CS
=
VIL
100
ns
Write Cycle Time
T
wP
10
ms
5V, 25C, Page Mode
Endurance**
1M
write cycles
Note** : The parameter is characterized and isn't 100% tested.
FIGURE 1. AC TEST CONDITIONS
632 ohm
DO
1.247V
(1 TTL Gate Load)
100PF
Instruction Set
Address
Input Data
Instruction
Start
Bit
OP
Code
8
16
8
16
READ 1
10
A
7
- A
0
A
6
- A
0
WEN (Write Enable)
1
00
11 XXXXXX
11XXXXX
WRITE 1
01
A
7
- A
0
A
6
- A
0
D
7
D
0
D
15
- D
0
WRALL (Write All Registers)
1
00
01XXXXXX
01XXXXX
D
7
D
0
D
15
- D
0
WDS (Write Disable)
1
00
00 XXXXXX
00XXXXX
ERASE 1
11
A
7
- A
0
A
6
- A
0
ERAL (Erase All Registers)
1
00
10 XXXXXX
10XXXXX
2048-bits Serial Electrically Erasable PROM
AM93LC56
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
4/10
ATC
Pin Capacitance
**
(Ta=25
C , f=1MH
z
)
Symbol
Parameter
Max
Units
C
OUT
Output
capacitance
5
pF
C
IN
Input
capacitance
5
pF
Note ** : The parameter is characterized and isn't 100% tested.
Functional Descriptions
Applications
The AM93LC56 is ideal for high volume applications
requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package.
Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings
such as LAN cards, monitors and MODEM.
Endurance and Data Retention
The AM93LC56 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRALL, EARSE and ERALL). It provides 40 years
of secure data retention.
Device Operation
The AM93LC56 is controlled by seven 10-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (7 bits), and data, if appropriate.
The clock signal (SK) may be halted at any time and
the AM93LC56 will remain in its last state. This
allows full static flexibility and maximum power
conservation.
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into a
8-bit or 16-bit serial shift register. (Please note that
one logical "0" bit precedes the actual 8-bit or 16-bit
output data string.) The output on DO changes
during the rising edge transitions of SK. (Shown in
Figure 3.)
Auto Increment Read Operations
Sequential read is possible, since the AM93LC56
has been designed to output a continuous stream of
memory content in response to a single read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Write Enable (WEN)
Before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done, the WRITE
ENABLE (WEN) instruction must be executed first.
When Vcc is applied, this device powers up in the
WRITE DISABLE state. The device then remains in
a WRITE DISABLE state until a WEN instruction is
executed. Thereafter the device remains enabled
until a WDS instruction is executed or until Vcc is
removed. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 4.)
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all
programming capabilities. This protects the entire
part against accidental modification of data until a
WEN instruction is executed. (When Vcc is applied,
this part powers up in the WRITE DISABLE state.)
To protect data, a WDS instruction should be
executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 5.)
2048-bits Serial Electrically Erasable PROM
AM93LC56
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
5/10
ATC
Functional Description (Continued)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought
LOW. The falling edge of CS initiates the self-timed
programming cycle.
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6)
Note: The combination of CS HIGH, DI HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
Before a WRITE instruction can be executed, the
device must be in the WRITE ENABLE (WEN) state.
Write All (WRALL)
The Write All (WRALL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRALL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7.)
As with the WRITE instruction, if CS is brought
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7.)
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to indicate
the READ/BUSY status of the chip. To explain this,
a logical "0" indicates the programming is still in
progress while a logical "1" indicates the erase cycle
is complete and the part is ready for another
instruction. (Shown in Figure 8.)
Erase All (ERALL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (Shown in
Figure 9.)
Security Consideration
To protect the entire part against accidental
modification of data, each programming instruction
(WRITE, WRALL, ERASE, and ERALL) must satisfy
two conditions before user initiate self-timed
programming cycle (the falling edge of CS). One is
that the AM93LC56 is at WEN status. The other is
that the Vcc value must exceed a lock-out value
which can be adjusted by ANALOG TECHNOLOGY
INC.
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