AP2002
Synchronous PWM Controller
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.2 Apr 14, 2004
1/7
Features
- Single or Dual Supply Application
- 0.8V + 1.0% Voltage Reference.
- Fast transient response.
- Synchronous operation for high efficiency (95%)
- On-chip power good, OVP protect.
- Small size with minimum external components
- Soft Start and enable functions
- Industrial temperature range
- Under Voltage Lockout function
- SOP-14L package
Applications
- Microprocessor core supply
- Low cost synchronous applications
- Voltage Regulator Modules (VRM)
- DDR termination supplies
- Networking power supplies
- Sequenced power supplies
General Description
The AP2002 is a low-cost, full featured, and
synchronous voltage-mode controller designed for
use in single ended power supply applications
where efficiency is of primary concern. This
synchronous operation allows the elimination of
heat sinks in many applications. The AP2002 is
ideal for implementing DC/DC converters that is
needed for the power advanced microprocessors in
low cost systems, or in distributed power
applications where efficiency is important. Internal
level-shift, high-side drive circuitry, and preset
shoot-thru control, allows the use of inexpensive
N-channel power switches.
AP2002 features include temperature compensated
voltage reference, an internal 200Khz virtual
frequency oscillator, under voltage lockout
protection, soft-start function and current sense
comparator circuitry. Power good signaling,
shutdown, and over voltage protection are also
provided by AP2002.
Pin Assignment
SOP-14L
1
(Top View)
VCC
PWRGD
OVP
OCSET
PHASE
DRVH
PGND
DRVL
BSTL
BSTH
SENSE
COMP
GND
SS/SHDN
AP2002
2
3
4
5
6
7
8
9
10
11
12
13
14
Ordering Information
AP2002 X X X
Package
Packing
S: SOP-14L
Blank : Tube
A : Taping
Lead Free
Blank : Normal
L : Lead Free Package
Pin Descriptions
Name
Description
VCC Chip
supply
voltage
PWRGD
Logic high indicates correct output
voltage (open drain output)
OVP Over
voltage
protection
OCSET
Sets the converter over-current trip
point
PHASE
Input from the phase node between
the MOSFETs
DRVH
High side driver output
PGND Power
ground
DRVL
Low side driver output
BSTL
Bootstrap, low side driver
BSTH
Bootstrap, high side driver
SENSE
Voltage sense input
COMP Compensation
pin
SS/ SHDN
Soft start, a capacitor to ground sets
the slow start time
GND Signal
ground
AP2002
Synchronous PWM Controller
Anachip Corp.
www.anachip.com.tw Rev. 0.2 Apr 14, 2004
2/7
Block Diagram
DRVH
Cross
Current
Control
DRVL
VCC
GND
PWRGD
SS/SHDN
OVP
SENSE
OCSET
PHASE
BSTH
DRVH
BSTL
PGND
DRVL
200uA
Over Current
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
One-Shot
Oscillator
PWM
Foult
Ob
S
R
0.6V
0.5V
Vcc
10uA
2uA
Vbg
Error Amp
Vcc
Under
Voltage
Vbg
+10%
- 10%
+20%
0.8V
VCC
COMP
Absolute Maximum Ratings
Symbol
Parameter
Max.
Unit
V
IN
VCC, BSTL to GND
-1 to 14
V
PGND to GND
+ 0.5
V
PHASE to GND
-1 to 18
V
V
PHASE
BSTH to PHASE
14
V
JC
Thermal Resistance Junction to Case
45
o
C/W
JA
Thermal Resistance Junction to Ambient
115
o
C/W
T
OP
Operating Temperature Range
-40 to +85
o
C
T
ST
Storage Temperature Range
-65 to +150
o
C
T
LEAD
Lead Temperature (Soldering) 10 Sec.
300
o
C
AP2002
Synchronous PWM Controller
Anachip Corp.
www.anachip.com.tw Rev. 0.2 Apr 14, 2004
3/7
Electrical Characteristics
Unless specified: V
CC
=
4.75V to 12.6V; GND = PGND = 0V; FB = V
O
; V
BSTL
= 12V; V
BSTH-PHASE
= 12V; T
J
= 25
o
C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supply
V
CC
Supply
Voltage
V
CC
4.2
12.6
V
I
CC
Supply
Current
6 10 mA
V
LINE
Line Regulation
VO = 2.5V
0.5
%
Error Amplifier
A
OL
Gain
(A
OL
)
50 dB
I
B
Input
Bias
5 8 uA
Oscillator
F
OSC
Oscillator
Frequency
180 200 220 KHz
DC
MAX
Oscillator Max Duty Cycle
90
95
%
MOSFET Drivers
I
DRVH
DRVH
Source/Sink
V
BSTH
V
DRVH
=4.5V
V
DRVH
V
PHASE
= 2V
1 A
I
DRVL
DRVL
Source/Sink
V
BSTH
V
DRVL
= 4.5V
V
DRVL
V
PGND
= 2V
1 A
Protection
D
TH
OVP
Threshold
20 %
I
OVP
OVP
Source
Current V
OVP
= 3V
10
mA
D
PG
Power
Good
Threshold
88 112 %
T
DEAD
Dead
Time
45 100 nS
I
OCSET
Over Current Set Isink
2.0V < V
OCSET
<
12V
180 200 220 uA
Reference
Reference Voltage
0.792
0.8
0.808
V
V
REF
Accuracy
0
o
C to 70
o
C
-1 +
1
%
Soft Start
I
SSC
Charge
Current
V
SS
= 1.5V
8.0
10
12
uA
I
SSD
Discharge
Current
V
SS
= 1.5V
1.3
2
2.7
uA
Under voltage lockout (UVLO)
V
UT
Upper threshold voltage
(V
CC
)
4.2
4.4 V
V
LWT
Lower threshold voltage
(V
CC
)
4.0 V
V
HT
Hysteresis
(V
CC
)
I
O(REF)
= 0.1mA
T
A
= 25C
200 mV
Note 1. Specification refers to Typical Application Circuit.
Note 2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
AP2002
Synchronous PWM Controller
Anachip Corp.
www.anachip.com.tw Rev. 0.2 Apr 14, 2004
4/7
Typical Application Circuit
(1)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
R4
10
C2
0.1
C1
0.1
R2
10k
R1
1k
+5V
PWRGD
OVP
R3
1k
D1
Option
VCC
GND
PWRGD SS/SHDN
OVP
COMP
OCSET
SENSE
PHASE
BSTH
DRVH
BSTL
PGND
DRVL
C3
0.1
SHDN
C4
R5
1.2O
R6
1.2O
Q1
PFD3000
Q2
PFD3000
L1
3.3uH
C10
0.1
C11
680/
16V
C12
680/
16V
C13
680/
16V
C14
680/
16V
Vout=2.5V
+
-
V
IN
5V/12V
+
-
C8
C7
C6
680/
16V
C5
0.1
R8
120
R9
270*
Note:
*Vout
=Vref x (1+R9/R8)
5V & 12V dual input circuit
680/
16V
680/
16V
+12V
47k 18nF
R10
4.7O
R7
C9
0.1u
(2)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
R4
10
C2
0.1
C1
0.1
R2
10k
R1
1k
+5V
PWRGD
OVP
R3
1k
D1
Option
VCC
GND
PWRGD SS/SHDN
OVP
COMP
OCSET
SENSE
PHASE
BSTH
DRVH
BSTL
PGND
DRVL
C3
0.1
SHDN
D2
C4
R5
1.2
R6
1.2
Q1
PFD3000
Q2
PFD3000
C9
0.1
L1
3.3uH
C10
0.1
C11
680/
16V
C12
C13
C14 Vout=2.5V*
+
-
V
IN
5V or 12V
+
-
C8
680/
16V
C7
680/
16V
C6
680/
16V
C5
0.1
R8
120
R9
270*
Note:
* Vout=Vref x (1+R9/R8)
5V or 12V input with Bootstrapped BSTH
47k 18nF
680/
16V
680/
16V
680/
16V
R10
4.7
R7
C9
0.1u
AP2002
Synchronous PWM Controller
Anachip Corp.
www.anachip.com.tw Rev. 0.2 Apr 14, 2004
5/7
Function Description
Synchronous Buck Converter
Primary V
CORE
power is provided by a synchronous,
voltage-mode pulse width modulated (PWM)
controller. This section has all the features required
to build a high efficiency synchronous buck
converter, including "Power Good" flag, shutdown,
and cycle-by-cycle current limit.
The output voltage of the synchronous converter is
set and controlled by the output of the error
amplifier. The external resistive divider reference
voltage is derived from an internal trimmed
band-gap voltage reference. The inverting input of
the error amplifier receives its voltage from the
SENSE pin.
The internal oscillator uses an on-chip capacitor
and trimmed precision current sources to set the
oscillation frequency to 200KHz. The triangular
output of the oscillator sets the reference voltage at
the inverting input of the comparator. When the
oscillator output voltage drops below the error
amplifier output voltage, the comparator output
goes high. This pulls DRVL low, turning off the
low-side FET, and DRVH is pulled high, turning on
the high-side FET (once the cross-current control
allows it). When the oscillator voltage rises back
above the error amplifier output voltage, the
comparator output goes low. This pulls DRVH low,
turning off the high-side FET, and DRVL is pulled
high, turning on the low-side FET (once the
cross-current control allows it).
As SENSE increases, the output voltage of the
error amplifier decreases. This causes a reduction
in the on-time of the high-side MOSFET connected
to DRVH, hence lowering the output voltage.
Under Voltage Lockout
The under voltage lockout circuit of the AP2002
assures that the high-side MOSFET driver outputs
remain in the off state whenever the supply voltage
drops below set parameters. Lockout occurs if V
CC
falls below 4.1V. Normal operation resumes once
V
CC
rises above 4.2V.
Over-Voltage Protection
The over-voltage protection pin (OVP) is high only
when the voltage at SENSE is 20% higher than the
target value programmed by the external resistor
divider. The OVP pin is internally connected to a
PNP's collector.
Power Good
The power good function is to confirm that the
regulator outputs are within +/- 10% of the
programmed level. PWRGD remains high as long
as this condition is met. PWRGD is connected to an
internal open collector NPN transistor.
Soft Start
Initially, SS/ SHDN sources 10uA of current to
charge an external capacitor. The outputs of the
error amplifiers are clamped to a voltage
proportional to the voltage on SS/ SHDN . This limits
the on-time of the high-side MOSFET, thus leading
to a controlled ramp-up of the output voltages.
R
DS(ON)
Current Limiting
The current limit threshold is setting by connecting
an external resistor from V
CC
supply to OCSET.
The voltage drop across this resistor is due to the
200uA internal sink sets the voltage at the pin.
This voltage is compared to the voltage at the
PHASE node. This comparison is made only when
the high-side drive is high to avoid false current limit
triggering due to un-contributing measurements
from the MOSFETs off-voltage. When the voltage at
PHASE is less than the voltage at OCSET, an
over-current condition occurs and the soft start
cycle is initiated. The synchronous switch turns off
and SS/ SHDN starts to sink 2uA. When
SS/ SHDN reaches 0.8V, it then starts to source
10uA and a new cycle begins.
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