This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

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PEELTM 22CV10A -7/-10/-15/-25

CMOS Programmable Electrically Erasable Logic Device

Features

High Speed/Low Power

- Speeds ranging from 7ns to 25ns

- Power as low as 30mA at 25MHz

Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Development/Programmer Support

- Third party software and programmers

- Anachip PLACE Development Software

General Description

The PEELTM22CV10A is a Programmable Electrically Eras-

able Logic (PEELTM) device providing an attractive alterna-

tive to ordinary PLDs. The PEELTM22CV10A offers the

performance, flexibility, ease of design and production

practicality needed by logic designers today. The

PEELTM22CV10A is available in 24-pin DIP, SOIC, TSSOP

and 28-pin PLCC packages (see Figure 1), with speeds

ranging from 7ns to 25ns and with power consumption as low

as 30mA. EE-reprogrammability provides the conve- nience

of instant reprogramming for development and a reusable

production inventory, minimizing the impact of

programming changes or errors. EE-reprogrammability

Architectural Flexibility

- 132 product term X 44 input AND array

- Up to 22 inputs and 10 outputs

- Up to 12 configurations per macrocell

- Synchronous preset, asynchronous clear

- Independent output enables

- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC

Application Versatility

- Replaces random logic

- Pin and JEDEC compatible with 22V10

- Enhanced Architecture fits more logic

than ordinary PLDs

also improves factory testability, thus ensuring the highest

quality possible. The PEELTM22CV10A is JEDEC file com-

patible with standard 22V10 PLDs. Eight additional configu-

rations per macrocell (a total of 12) are also available by

using the "+" software/programming option (i.e., 22CV10A+

& 22CV10A++). The additional macrocell configurations

allow more logic to be put into every design. Programming

and development support for the PEELTM22CV10A are pro-

vided by popular third-party programmers and develop-

ment software. Anachip also offers free PLACE

development software.

Figure 1. Pin Configuration Figure 2. Block Diagram

I/CLK 1

I 2

I 3

I 4

I 5

I 6

I 7

I 8

I 9

I 10

I 11

GND 12

24 VCC

23 I/O

22 I/O

21 I/O

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 I

DIP

TSSOP

PLCC

*Optional extra ground pin for

-7/I-7 speed grade.

SOIC

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Function Description

The PEELTM22CV10A implements logic functions as sum-

of-products expressions in a programmable-AND/ fixed-OR

logic array. User-defined functions are created by program-

ming the connections of input signals into the array. User-

configurable output structures in the form of I/O macrocells

further increase logic flexibility.

Architecture Overview

The PEELTM22CV10A architecture is illustrated in the block

diagram of Figure 2. Twelve dedicated inputs and 10 I/Os

provide up to 22 inputs and 10 outputs for creation of logic

functions. At the core of the device is a programmable elec-

trically-erasable AND array which drives a fixed OR array.

With this structure, the PEELTM22CV10A can implement up

to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is an I/O mac-

rocell which can be independently programmed to one of 4

different configurations. The programmable macrocells

allow each I/O to create sequential or combinatorial logic

functions with either active-high or active-low polarity.

AND/OR Logic Array

The programmable AND array of the PEELTM22CV10A

(shown in Figure 3) is formed by input lines intersecting

product terms. The input lines and product terms are used as

follows:

44 Input Lines:

24 input lines carry the true and complement
of the signals applied to the 12 input pins
20 additional lines carry the true and complement
values of feedback or input signals from
the 10 I/Os

132 product terms:

120 product terms (arranged in 2 groups of 8,
10, 12, 14 and 16) used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous present term
1 global asynchronous clear term

At each input-line/product-term intersection there is an

EEPROM memory cell which determines whether or not

there is a logical connection at that intersection. Each prod-

uct term is essentially a 44-input AND gate. A product term

which is connected to both the true and complement of an

input signal will always be FALSE, and thus will not affect the

OR function that it drives. When all the connections on a

product term are opened, a "don't care" state exists and that

term will always be TRUE. When programming the

PEELTM22CV10A, the device programmer first performs a

bulk erase to remove the previous pattern. The erase cycle

opens every logical connection in the array. The device is

then configured to perform the user-defined function by

programming selected connections in the AND array. (Note

that PEELTM device programmers automatically program

the connections on unused product terms so that they will

have no effect on the output function.)

Variable Product Term Distribution

The PEELTM22CV10A provides 120 product terms to drive

the 10 OR functions. These product terms are distributed

among the outputs in groups of 8, 10, 12, 14 and 16 to form

logical sums (see Figure 3). This distribution allows opti-

mum use of device re-sources.

Programmable I/O Macrocell

The output macrocell provides complete control over the

architecture of each output. The ability to configure each

output independently permits users to tailor the configura-

tion of the PEELTM22CV10A to the precise requirements of

their designs.

Macrocell Architecture

Each I/O macrocell, as shown in Figure 4, consists of a D-

type flip-flop and two signal-select multiplexers. The config-

uration of each macrocell is determined by the two

EEPROM bits controlling these multiplexers (refer to Table
1). These bits determine output polarity and output type

(registered or non-registered). Equivalent circuits for the

four macro-cell configurations are illustrated in Figure 5.

Output Type

The signal from the OR array can be fed directly to the out-

put pin (combinatorial function) or latched in the D-type flip-

flop (registered function). The D-type flip-flop latches data on

the rising edge of the clock and is controlled by the glo- bal

preset and clear terms. When the synchronous preset term

is satisfied, the Q output of the register will be set HIGH at

the next rising edge of the clock input. Satisfying the

asynchronous clear term will set Q LOW, regardless of the

clock state. If both terms are satisfied simultaneously, the

clear will override the preset.

Output Polarity

Each macrocell can be configured to implement active-high

or active-low logic. Programmable polarity eliminates the

need for external inverters.

Output Enable

The output of each I/O macrocell can be enabled or dis-

abled under the control of its associated programmable

output enable product term. When the logical conditions

programmed on the output enable term are satisfied, the

output signal is propagated to the I/O pin. Otherwise, the

output buffer is driven into the high-impedance state.

Under the control of the output enable term, the I/O pin can

function as a dedicated input, a dedicated output, or a bi-

directional I/O. Opening every connection on the output

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enable term will permanently enable the output buffer and

yield a dedicated output. Conversely, if every connection is

intact, the enable term will always be logically false and the

I/O will function as a dedicated input.

Input/Feedback Select

When configuring an I/O macrocell to implement a regis-

tered function (configurations 1 and 2 in Figure 5), the Q

output of the flip-flop drives the feedback term. When con-

figuring an I/O macrocell to implement a combinatorial

function (configurations 3 and 4 in Figure 5), the feedback

signal is taken from the I/O pin. In this case, the pin can be

used as a dedicated input or a bi-directional I/O. (Refer also

to Table 1.)

Additional Macro Cell Configurations

Besides the standard four-configuration macrocell shown in

Figure 5, each PEELTM22CV10A provides an additional

eight configurations that can be used to increase design

flexibility. The configurations are the same as provided by the

PEELTM18CV8 and PEELTM22CV10AZ. However, to

maintain JEDEC file compatibility with standard 22V10

PLDs the additional configurations can only be utilized by

specifying the PEELTM22CV10A+ and PEEL22CV10A++ for

logic assembly and programming. To reference these

additional configurations please refer to the specifications at

the end of this data sheet.

Design Security

The PEELTM22CV10A provides a special EEPROM secu-

rity bit that prevents unauthorized reading or copying of

designs programmed into the device. The security bit is set

by the PLD programmer, either at the conclusion of the pro-

gramming cycle or as a separate step after the device has

been programmed. Once the security bit is set, it is impos-

sible to verify (read) or program the PEELTM until the entire

device has first been erased with the bulk-erase function.

Signature Word

The signature word feature allows a 24-bit code to be pro-
grammed into the PEELTM22CV10A if the
PEELTM22CV10A+ software option is used. Also, the sig-
nature word feature allows a 64-bit code to be programmed
into the PEELTM22CV10A if the PEELTM22CV10A++ soft-
ware option is used. The code can be read back even after
the security bit has been set. The signature word can be
used to identify the pattern programmed into the device or to
record the design revision, etc.

Figure 4. Block Diagram of the PEELTM 22CV10A I/O Macrocell.

Электронный компонент: PEEL22CV10AJ-7L