10/2001
ARA2008
Reverse Amplifier with Step Attenuator
ADVANCED PRODUCT INFORMATION - Rev 0.0
FEATURES
Low cost integrated amplifier with step
attenuator
Attenuation Range: 0-58 dB, adjustable in
1dB increments via a 3 wire serial control
Meets DOCSIS distortion requirements at
+60dBmV output signal level
Low distortion and low noise
Frequency range: 5-100MHz
5 Volt operation
-40 to +85
0
C temperature range
APPLICATIONS
MCNS/DOCSIS Compliant Cable Modems
CATV Interactive Set-Top Box
Telephony over Cable Systems
OpenCable Set-Top Box
Residential Gateway
The ARA2008 is designed to provide the reverse path
amplification and output level control functions in a
CATV Set-Top Box or Cable Modem. It incorporates
a digitally controlled precision step attenuator that is
preceded by an ultra low noise amplifier stage, and
followed by an ultra-linear output driver amplifier. This
device uses a balanced circuit design that exceeds
the MCNS/DOCSIS requirement for harmonic
performance at a +60dBmV output level while only
requiring a single polarity +5V supply. Both the input
and output are matched to 75 ohms with an
appropriate transformer. The precision attenuator
provides up to 58 dB of attenuation in 1 dB increments
via a three-wire serial interface. With external passive
components, this device meets IEC 1000-4-12 and
ANSI/IEEE C62.41-1991 100KHz ringwave tests, as
well as IEC1000-4-5 1.2/50mS surge tests. The
ARA2008 is offered in a 20-pin SSOP package.
PRODUCT DESCRIPTION
Figure 1. Cable Modem or Set Top Box Application Diagram
20 Pin SSOP Package
Diplexer
ARA2008
SAW
Filter
Double-
Conversion
Tuner
MAC
Upstream
QPSK/16QAM
Modulator
QAM Receiver
with FEC
Balun
Low Pass
Filter
Transmit Enable/Disable
Enable
Data
Clock
Microcontroller
with Ethernet
MAC
RAM
ROM
10Base-T
Transceiver
RJ45
Connector
Clock
Clock
Data
Data
54-860 MHz
44 MHz
5-42 MHz
2
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
ARA2008
Figure 2: Functional Block Diagram
Figure 3: Pin Out - SSOP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
19
18
17
16
15
GND
GND
RF
OUT
(-)
RF
IN
(+)
CLOCK
DATA
V
DD1
ENBL
RF
IN
(-)
N/C
C
EXT2
N/C
GND
RF
OUT
(+)
C
EXT1
TXEN
GND
GND
GND
V
DD2
32 dB
1 dB
2 dB
4 dB
8 dB
16 dB
Buffer
Control Latch
6-bit Shift
Register
8
RF
IN
(+)
RF
IN
(-)
ENBL
DATA
CLOCK
RF
OUT
(+)
RF
OUT
(-)
TXEN
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
3
ARA2008
Table 1: Pin Description - SSOP Package
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
1
D
N
G
d
n
u
o
r
G
1
1
D
N
G
d
n
u
o
r
G
2
V
1
D
D
y
l
p
p
u
S
2
1
C
/
N
n
o
it
c
e
n
n
o
c
o
N
3
D
N
G
d
n
u
o
r
G
3
1
C
/
N
n
o
it
c
e
n
n
o
c
o
N
4
D
N
G
d
n
u
o
r
G
4
1
C
2
T
X
E
r
o
ti
c
a
p
a
C
l
a
n
r
e
t
x
E
5
F
R
N
I
)
+
(
t
u
p
n
I
)
+
(
F
R
5
1
F
R
T
U
O
)-
(
t
u
p
t
u
O
)-
(
F
R
6
F
R
N
I
)-
(
t
u
p
n
I
)-
(
F
R
6
1
F
R
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
F
R
7
D
N
G
d
n
u
o
r
G
7
1
C
1
T
X
E
r
o
ti
c
a
p
a
C
l
a
n
r
e
t
x
E
8
L
B
N
E
e
l
b
a
n
E
8
1
N
E
X
T
e
l
b
a
n
E
ti
m
s
n
a
r
T
9
A
T
A
D
a
t
a
D
9
1
V
2
D
D
y
l
p
p
u
S
0
1
K
C
O
L
C
k
c
o
l
C
0
2
D
N
G
d
n
u
o
r
G
4
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
ARA2008
ELECTRICAL CHARACTERISTICS
R
E
T
E
M
A
R
A
P
N
I
M
X
A
M
T
I
N
U
V
:
y
l
p
p
u
S
DD
)
9
1
,
6
1
,
5
1
,
2
s
n
i
p
(
0
9
C
D
V
F
R
s
t
u
p
n
I
t
a
r
e
w
o
P
s
n
i
p
(
6
,
5
)
-
0
6
+
V
m
B
d
)
0
1
,
9
,
8
s
n
i
p
(
e
c
a
fr
e
t
n
I
l
a
ti
g
i
D
5
.
0
-
V
DD
5
.
0
+
V
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
5
-
0
0
2
+
0
C
e
r
u
t
a
r
e
p
m
e
T
g
n
ir
e
d
l
o
S
-
0
6
2
0
C
e
m
i
T
g
n
ir
e
d
l
o
S
-
5
c
e
S
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
t
n
e
r
r
u
C
y
l
p
p
u
S
l
a
t
o
T
)
9
1
,
6
1
,
5
1
,
2
s
n
i
p
(
-
-
5
3
1
5
1
-
-
A
m
)
h
g
i
h
N
E
X
T
(
d
e
l
b
a
n
e
x
T
)
w
o
l
N
E
X
T
(
d
e
l
b
a
s
i
d
x
T
n
o
it
p
m
u
s
n
o
C
r
e
w
o
P
l
a
t
o
T
-
-
5
7
6
5
7
-
-
W
m
)
h
g
i
h
N
E
X
T
(
d
e
l
b
a
n
e
x
T
)
w
o
l
N
E
X
T
(
d
e
l
b
a
s
i
d
x
T
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
V
:
y
l
p
p
u
S
DD
)
9
1
,
6
1
,
5
1
,
2
s
n
i
p
(
5
.
4
5
7
C
D
V
)
0
1
,
9
,
8
s
n
i
p
(
e
c
a
fr
e
t
n
I
l
a
ti
g
i
D
0
-
V
DD
V
e
r
u
t
a
r
e
p
m
e
T
e
s
a
C
0
4
-
5
2
5
8
0
C
Table 4: DC Electrical Specifications
T
A
=25
C; V
DD
= +5.0 VDC
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for
extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
Table 5: Digital Interface Specifications
T
A
=25
C; V
DD
= +5.0 VDC
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
V
:
e
g
a
tl
o
V
t
u
p
n
I
h
g
i
H
c
i
g
o
L
IN
,
HIGH
0
.
2
-
V
DD
V
V
:
e
g
a
tl
o
V
t
u
p
n
I
w
o
L
c
i
g
o
L
IN
,
LOW
0
-
8
.
0
V
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
5
ARA2008
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
)
z
H
M
0
1
(
n
i
a
G
-
9
2
-
B
d
g
n
it
t
e
s
n
o
it
a
u
n
e
tt
a
B
d
0
s
s
e
n
t
a
l
F
n
i
a
G
-
5
.
1
-
B
d
z
H
M
5
6
o
t
5
e
r
u
t
a
r
e
p
m
e
T
r
e
v
o
n
o
it
a
ir
a
V
n
i
a
G
-
6
0
0
.
0
-
-
C
/
B
d
e
z
i
S
p
e
t
S
n
o
it
a
u
n
e
tt
A
-
1
-
B
d
c
i
n
o
t
o
n
o
M
n
o
it
a
u
n
e
tt
A
m
u
m
i
x
a
M
8
5
-
-
B
d
2
d
n
)
z
H
M
0
1
(
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
-
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
3
d
r
)
z
H
M
0
1
(
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
-
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
3
d
r
t
p
e
c
r
e
t
n
I
t
u
p
t
u
O
r
e
d
r
O
8
7
-
-
V
m
B
d
t
n
i
o
P
n
o
i
s
s
e
r
p
m
o
C
n
i
a
G
B
d
1
-
5
.
8
6
-
V
m
B
d
e
r
u
g
i
F
e
s
i
o
N
-
0
.
3
-
B
d
s
s
o
l
n
u
l
a
b
t
u
p
n
i
s
e
d
u
l
c
n
I
r
e
w
o
P
e
s
i
o
N
t
u
p
t
u
O
.t
e
S
.
n
e
tt
A
.
n
i
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
.t
e
S
.
n
e
tt
A
.
x
a
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
-
-
-
-
5
.
8
3
-
8
.
3
5
-
V
m
B
d
h
t
d
i
w
d
n
a
b
z
H
k
0
6
1
y
n
A
z
H
M
2
4
o
t
5
m
o
rf
e
d
o
m
e
l
b
a
s
i
d
x
T
n
i
)
z
H
M
5
4
(
n
o
it
a
l
o
s
I
-
0
6
-
B
d
)
d
e
l
b
a
n
e
x
T
(
e
c
n
a
d
e
p
m
I
t
u
p
n
I
l
a
it
n
e
r
e
ff
i
D
-
0
0
3
-
s
m
h
O
)
d
e
l
b
a
n
e
x
T
(
e
c
n
a
d
e
p
m
I
t
u
p
n
I
-
5
7
-
s
m
h
O
r
e
m
r
o
f
s
n
a
rt
h
ti
w
)
s
m
h
O
5
7
(
s
s
o
L
n
r
u
t
e
R
t
u
p
n
I
-
5
1
-
-
B
d
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
l
a
it
n
e
r
e
ff
i
D
-
0
0
3
-
s
m
h
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
-
5
7
-
s
m
h
O
r
e
m
r
o
f
s
n
a
rt
h
ti
w
)
s
m
h
O
5
7
(
s
s
o
L
n
r
u
t
e
R
t
u
p
t
u
O
-
5
1
-
-
B
d
t
n
e
i
s
n
a
r
T
e
g
a
tl
o
V
t
u
p
t
u
O
e
l
b
a
s
i
d
x
T
/
e
l
b
a
n
e
x
T
-
-
-
4
0
0
1
7
p
-
p
V
m
g
n
it
t
e
s
r
o
t
a
u
n
e
tt
a
B
d
0
g
n
it
t
e
s
r
o
t
a
u
n
e
tt
a
B
d
4
2
Table 6: AC Electrical Specifications
T
A
=25
C; V
DD
= +5.0 VDC
6
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
ARA2008
Table 7: Programming Word
T
I
B
A
T
A
D
D
5
D
4
D
3
D
2
D
1
D
0
e
u
l
a
V
5
P
4
P
3
P
2
P
1
P
0
P
LOGIC PROGRAMMING
Table 8: Data Description
Figure 4: Serial Data Input Timing
E
U
L
A
V
N
O
I
T
C
N
U
F
)
s
s
a
p
y
b
=
1
,
n
o
=
0
(
5
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
2
3
4
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
6
1
3
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
8
2
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
4
1
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
2
0
P
ti
B
r
o
t
a
u
n
e
tt
A
B
d
1
Programming Instructions
The programming word is set through a 6 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
DATA
CLOCK
ENBL
D
5
: MSB
D
4
D
3
D
2
D
1
D
0
: LSB
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
7
ARA2008
APPLICATION INFORMATION
Output Transformer
Matching the output of the ARA2008 to a 75 Ohm
load is accomplished using a 2:1 turns ratio
transformer. In addition to providing an impedance
transformation, this transformer provides the bias to
the output amplifier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the amplifiers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF
and DC power requirements without saturating the
core, and it must have adequate isolation and good
phase and amplitude balance. It also must operate
over the desired frequency and temperature range
for the intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Although the
ARA2008 has some built-in ESD protection, proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
8
ARA2008
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