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Электронный компонент: AWT1921

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08/2001
FEATURES
AWT1921
Integrated High Power Amp 1610 MHz
PRELIMINARY DATA SHEET - Rev 1.0
S11
SSOP-28
28 Pin Wide Body w/ Heat Slug
High Output Intercept Point
High Linearity
True Surface Mount Package
Internal Bias Circuit Requiring Nominal Input
Voltages + 10%
Low Cost
Off Chip Output Matching Circuit Allows
Application Optimization
PRODUCT DESCRIPTION
The AWT1921 is a four stage monolithic amplifier for
use in communication systems that require high gain
and output intercept point. The device has been
specifically designed for fixed satellite access
equipment and handset booster amplifier
applications.
Pin 1
Pin 28
Pin 14
Pin 15
GND
V
GS1
/RF
IN
V
D1
V
D2
GND
GND
GND
V
D3
V
D3
V
GS2
V
SS
V
GS3
GND
GND
GND
V
DD
V
REF
V
D4
V
D4
V
D4
V
D4
V
D4
V
D4
V
D4
V
D4
V
GS4
V
GS4
GND
Figure 1: Pin Layout
Table 1: Pin Description
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
-
1
,
4
1
,
1
,
8
2
,
5
g
u
l
s
D
N
G
d
n
u
o
r
G
F
R
d
n
a
C
A
2
V
1
S
G
F
R
&
N
I
t
u
p
n
I
F
R
&
l
a
n
i
m
r
e
t
e
t
a
G
e
g
a
t
S
t
s
ri
F
7
2
V
D
D
)
V
5
+
(t
i
u
c
ri
C
s
a
i
B
f
o
y
l
p
p
u
S
e
v
it
i
s
o
P
4
V
2
D
V
9
+
(
y
l
p
p
u
s
n
i
a
r
d
e
g
a
t
S
d
n
o
c
e
S
3
V
1
D
)
V
9
+
(
y
l
p
p
u
s
n
i
a
r
d
e
g
a
t
S
t
s
ri
F
8
,
7
,
6
,
5
D
N
G
d
n
u
o
r
g
e
c
r
u
o
S
e
g
a
t
S
d
n
o
c
e
S
d
n
a
t
s
ri
F
0
1
,
9
V
3
D
)
V
9
+
(
y
l
p
p
u
s
n
i
a
r
d
e
g
a
t
S
d
ri
h
T
1
1
V
2
S
G
l
a
n
i
m
r
e
T
e
t
a
G
e
g
a
t
S
d
n
o
c
e
S
6
2
V
F
E
R
)
V
5
+
(
n
i
P
l
o
rt
n
o
c
s
a
i
B
2
1
V
S
S
)
V
5
-(
ti
u
c
ri
C
s
a
i
B
r
o
f
y
l
p
p
u
S
e
v
it
a
g
e
N
3
1
V
3
S
G
l
a
n
i
m
r
e
t
e
t
a
G
e
g
a
t
S
d
ri
h
T
7
1
,
6
1
V
4
S
G
l
a
n
i
m
r
e
t
e
t
a
G
e
g
a
t
S
h
tr
u
o
F
5
2
-
8
1
V
4
D
F
R
&
)
V
9
+
(
y
l
p
p
u
s
n
i
a
r
d
e
g
a
t
S
h
tr
u
o
F
t
u
o
PRELIMINARY DATA SHEET - Rev 1.0
08/2001
2
AWT1921
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
y
c
n
e
u
q
e
r
F
0
1
6
1
5
.
6
2
6
1
z
H
M
t
u
p
t
u
O
r
e
w
o
P
5
3
6
3
m
B
d
y
c
n
e
i
c
if
f
E
d
e
d
d
A
r
e
w
o
P
-
5
2
%
n
i
a
G
)
3
(
7
2
0
3
B
d
R
P
C
A
)
3
(
z
H
M
0
3
7
.
0
z
H
M
3
2
.
1
-
-
5
2
8
2
-
0
0
1
c
B
d
s
c
i
n
o
m
r
a
H
d
n
2
d
r
3
h
t
4
-
-
-
5
4
-
2
5
-
5
4
-
c
B
d
s
t
u
p
t
u
o
s
u
o
ir
u
p
s
ll
a
c
B
d
0
6
-
:
y
ti
li
b
a
t
S
l
a
n
g
i
s
d
e
ri
s
e
d
o
t
e
v
it
a
l
e
r
-
-
1
:
3
ll
a
,
d
a
o
l
R
W
S
V
s
e
l
g
n
a
e
s
a
h
p
s
t
n
e
rr
u
C
y
l
p
p
u
S
s
a
i
B
I
S
S
I
F
E
R
I
D
D
-
-
-
5
1
5
5
1
A
m
s
t
n
e
rr
u
C
t
n
e
c
s
e
i
u
Q
I
1
Q
D
I
2
Q
D
I
3
Q
D
I
4
Q
D
-
-
-
-
0
6
0
9
0
5
1
0
0
2
-
-
-
-
A
m
s
s
o
L
n
r
u
t
e
R
t
u
p
n
I
-
1
1
-
B
d
s
s
e
n
t
a
l
F
n
i
a
G
)
3
(
P
@
T
U
O
m
B
d
5
3
+
=
-
8
.
0
-
B
d
e
c
n
a
t
s
i
s
e
R
l
a
m
r
e
h
T
)
4
(
-
5
.
4
-
W
/
C
Table 2: Electrical Specifications
(1)
(Pin with CDMA modulation, fo = 1610 1626.5 MHz, V
DS1
= V
DS2
= V
DS3
= V
DS4
= 9.0V,V
SS
= -5V,V
REF
=+5V,V
DD
=+5V, Tc=25C, 50 W System
(2)
)
ELECTRICAL CHARACTERISTICS
Notes:
1. As measured in ANADIGICS test fixture, see application section.
2. 50W Measurement system after off chip matching circuit, input terminated in 50W.
3. Measured at P
OUT
= +35 dBm
4. Thermal Resistance for junction to bottom of slug
OUT
SUP
D
D
D
D
P
V
I
I
I
I
Tc
Tj
jc
-
+
+
+
-
)
(
4
3
2
1
PRELIMINARY DATA SHEET - Rev 1.0
08/2001
3
AWT1921
Operating Temperature: - 30 to + 85
C
Storage Temperature: - 55 to +100
C
Table 3: Absolute Max Ratings
Stresses in excess of the absolute ratings may cause permanent
damage. Functional operation is not implied under these conditions.
Exposure to absolute ratings for extended periods of time may
adversely affect reliability.
N
I
P
E
M
A
N
G
N
I
T
A
R
X
A
M
N
I
P
E
M
A
N
G
N
I
T
A
R
X
A
M
2
V
D
D
C
D
V
7
+
1
1
V
F
E
R
C
D
V
7
+
3
F
R
N
I
m
B
d
0
2
+
2
1
V
S
S
C
D
V
7
-
5
,
4
V
1
D
C
D
V
0
1
+
-,
9
1
,
8
1
-,
1
2
,
0
2
-,
3
2
,
2
2
5
2
,
4
2
V
3
D
C
D
V
0
1
+
9
,
8
V
2
D
C
D
V
0
1
+
PRELIMINARY DATA SHEET - Rev 1.0
08/2001
4
AWT1921
PERFORMANCE DATA
15
20
25
30
35
40
-15
-10
-5
0
5
10
15
Pin (dBm)
0
10
20
30
40
50
60
70
80
90
Pout
Eff
34
35
36
37
38
39
40
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
Vsup(v)
Pout
* P
OUT
with CDMA Modulation
P
IN
= 10 dBm, with CDMA Modulation
Figure 2: ACPR @ P
OUT
= 35 dBm
Figure 3: ACPR @ P
OUT
= 35 dBm
Figure 5: P
OUT
vs Supply Voltage
Figure 4: P
OUT
& Eff vs Pin
PRELIMINARY DATA SHEET - Rev 1.0
08/2001
5
AWT1921
MARKER 2
1.615750000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 - 4.800000000 GHz
IMPEDANCE
CH 1
- S11
REFERENCE PLANE
6.3507 cm
0.100000000 GHz
3.225500000 GHz
4.800000000 GHz
542.467 m
45.066
7.790
164.733
34.621 j
-10.839 j
112.368 j
-244.870 j
1
3
4
1
2
3
4
MARKER 2
1.615750000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 - 4.800000000 GHz
CH 1
- S11
REFERENCE PLANE
6.3507 cm
0.100000000 GHz
3.225500000 GHz
4.800000000 GHz
4.443
46.485
13.359
6.663
86.992 j
8.658 j
-31.442 j
16.669 j
1
3
4
1
2
3
4
Impedance as seen by V
DS3
Impedance as seen by V
DS1
Impedance as seen by V
DS2
MARKER 2
1.615750000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 -
4.800000000 GHz
CH 1
- S11
REFERENCE PLANE
6.3507 cm
0.100000000 GHz
3.225500000 GHz
4.800000000 GHz
423.067 m
46.696
2.436
2.544
4.971 j
-381.126 jm
18.889 j
31.529 j
1
3
4
1
2
3
4
Impedance as seen by V
DS4
Figure 9: S11 Forward Reflection Impedance
Figure 8: S11 Forward Reflection Impedance
Figure 7: S11 Forward Reflection Impedance
Figure 6: S11 Forward Reflection Impedance