09/2003
AWT921
900 MHz Integrated Power Amp
Data Sheet - Rev 2.0
S11
SSOP-28
28 Pin Wide Body w/ Heat Slug
Figure 1: Block Diagram
FEATURES
PRODUCT DESCRIPTION
The AWT921 is a monolithic amplifier for use in
communication systems that require high gain and
output intercept point. This device has been
specifically designed for multi-carrier and micro-cell
base station applications. This device is
High Power Levels
High Efficiency
True Surface Mount Package With Integrated
Heat Slug
Internal Bias Circuit Requiring Nominal Input
Voltages +10%
Low Cost
Off Chip Output Matching Circuit Allows
Application Optimization
APPLICATIONS
Base Station Driver Amplifier
u-Cell Base Station Output Stage
Cellular Booster Amplifier
manufactured on a high power MESFET process
and has an on-chip bias circuit that does not require
highly regulated positive and negative supplies to
establish the proper operating point.
RFin
RFout
Bias Network
RFC
Bypass
RFC
Bypass
RFC
Bypass
Vd1
Vd2
Vd3
Vg3
M1
M2
M3
On Chip
Vg2
Vg1
Vref
Vdd
Rref
Vss
2
Data Sheet - Rev 2.0
09/2003
AWT921
Figure 2: Pinout (X-Ray Top View)
Table 1: Pin Description
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
5
1
,
4
1
,
1
g
u
l
s
,
8
2
D
N
G
d
n
u
o
r
G
F
R
d
n
a
C
A
2
V
1
S
G
l
a
n
i
m
r
e
T
e
t
a
G
e
g
a
t
S
t
s
r
i
F
3
V
D
D
ti
u
c
r
i
C
s
a
i
B
f
o
y
l
p
p
u
S
e
v
it
i
s
o
P
4
F
R
N
I
t
u
p
n
I
F
R
6
,
5
V
1
D
y
l
p
p
u
S
n
i
a
r
D
e
g
a
t
S
t
s
r
i
F
8
,
7
D
N
G
d
n
u
o
r
G
e
c
r
u
o
S
e
g
a
t
S
t
s
r
i
F
0
1
,
9
V
2
D
y
l
p
p
u
S
n
i
a
r
D
e
g
a
t
S
d
n
o
c
e
S
1
1
V
F
E
R
n
i
P
l
o
r
t
n
o
C
s
a
i
B
2
1
V
S
S
ti
u
c
r
i
C
s
a
i
B
r
o
f
y
l
p
p
u
S
e
v
it
a
g
e
N
3
1
V
2
S
G
l
a
n
i
m
r
e
T
e
t
a
G
e
g
a
t
S
d
n
o
c
e
S
7
1
,
6
1
V
3
S
G
l
a
n
i
m
r
e
T
e
t
a
G
e
g
a
t
S
d
r
i
h
T
5
2
-
8
1
V
3
D
F
R
&
y
l
p
p
u
S
n
i
a
r
D
e
g
a
t
s
d
r
i
h
T
T
U
O
7
2
,
6
2
C
/
N
d
e
t
c
e
n
n
o
C
t
o
N
Data Sheet - Rev 2.0
09/2003
AWT921
3
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Stresses in excess of the absolute ratings may cause permanent
damage. Functional operation is not implied under these conditions.
Exposure to absolute ratings for extended periods of time may
adversely affect reliability.
Table 3: Operating Ranges
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specifications.
R
E
T
E
M
A
R
A
P
N
I
M
X
A
M
T
I
N
U
V
D
D
0
7
+
V
C
D
F
R
N
I
0
0
2
+
m
B
d
V
(
y
l
p
p
u
S
e
g
a
t
S
t
s
1
1
D
)
0
0
1
+
V
C
D
V
(
y
l
p
p
u
S
e
g
a
t
S
d
n
2
2
D
)
0
0
1
+
V
C
D
V
(
e
g
a
tl
o
V
e
g
a
t
S
d
r
3
3
D
)
0
0
1
+
V
C
D
V
(
y
l
p
p
u
S
e
v
it
a
g
e
N
S
S
)
7
-
0
V
C
D
V
(
e
g
a
tl
o
V
e
c
n
e
r
e
f
e
R
F
E
R
)
0
7
+
V
C
D
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
5
-
0
0
1
+
C
e
r
u
t
a
r
e
p
m
e
T
g
n
it
a
r
e
p
O
0
3
-
5
8
+
C
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
y
c
n
e
u
q
e
r
F
g
n
it
a
r
e
p
O
5
2
9
-
0
6
9
z
H
M
F
R
N
I
0
-
4
1
+
m
B
d
V
(
y
l
p
p
u
S
e
g
a
t
S
t
s
1
1
D
)
0
5
.
8
+
9
+
V
C
D
V
(
y
l
p
p
u
S
e
g
a
t
S
d
n
2
2
D
)
0
5
.
8
+
9
+
V
C
D
V
(
e
g
a
tl
o
V
e
g
a
t
S
d
r
3
3
D
)
0
5
.
8
+
9
+
V
C
D
V
(
e
g
a
tl
o
V
e
c
n
e
r
e
f
e
R
F
E
R
)
0
5
+
7
+
V
C
D
V
(
y
l
p
p
u
S
e
v
it
a
g
e
N
S
S
)
7
-
3
-
7
.
2
-
V
C
D
e
r
u
t
a
r
e
p
m
e
T
g
n
it
a
r
e
p
O
0
3
-
-
5
8
+
C
4
Data Sheet - Rev 2.0
09/2003
AWT921
Table 4: Electrical Specifications
(1)
( Pin = +12dBm, fo = 925-960 MHz, Vds1=Vds2=Vds3=8.5V, V
SS
= -5 V,
V
REF
= +25 V, V
DD
= +5 V, T
C
= +25 C, 50
system
(2)
)
Notes:
(1) As measured in ANADIGICS test fixture, see application section.
(2) 50
Measurement system after off chip matching circuit, input terminated in 50
.
(3) Measured at P
OUT
=+ 39 dBm.
(4) Thermal resistance for junction to bottom of slug.
jc = (Tj-Tc)/((I
D1
+I
D2
+I
D3
)*V
SUP
- P
OUT
)
R
E
T
E
M
A
R
A
P
L
O
B
M
Y
S
N
I
M
P
Y
T
X
A
M
T
I
N
U
y
c
n
e
u
q
e
r
F
o
f
5
2
9
-
0
6
9
z
H
M
t
u
p
t
u
O
r
e
w
o
P
P
T
U
O
-
9
3
+
-
m
B
d
y
c
n
e
i
c
if
f
E
d
e
d
d
A
r
e
w
o
P
F
F
E
-
0
4
-
%
n
i
a
G
P
@
OUT
m
B
d
9
3
+
=
P
@
OUT
m
B
d
0
3
+
=
G
P
-
-
7
2
1
3
-
-
B
d
n
o
m
r
a
H
s
c
i
)
3
(
d
n
2
d
r
3
h
t
4
-
-
-
7
3
7
4
0
5
-
-
-
c
B
d
ll
a
c
B
d
0
6
-
:
y
ti
li
b
a
t
S
o
t
e
v
it
a
l
e
r
s
t
u
p
t
u
o
s
u
o
ir
u
p
s
l
a
n
g
i
s
d
e
r
i
s
e
d
-
-
1
:
3
-
R
W
S
V
ll
a
,
d
a
o
l
e
s
a
h
p
s
e
l
g
n
a
s
t
n
e
r
r
u
C
y
l
p
p
u
S
s
a
i
B
I
S
S
I
F
E
R
I
D
D
-
-
-
8
2
.
1
8
-
-
-
A
m
s
t
n
e
r
r
u
C
t
n
e
c
s
e
i
u
Q
I
1
Q
D
I
2
Q
D
I
3
Q
D
-
-
-
0
0
1
0
5
2
0
0
2
-
-
-
A
m
s
s
o
L
n
r
u
t
e
R
t
u
p
n
I
-
0
1
-
-
B
d
s
s
e
n
t
a
l
F
n
i
a
G
P
@
T
U
O
m
B
d
9
3
+
=
P
@
T
U
O
m
B
d
0
3
+
=
G
P
5
.
0
5
.
0
-
-
-
-
B
d
e
c
n
a
t
s
i
s
e
R
l
a
m
r
e
h
T
)
4
(
-
5
.
4
-
W
/
C
Data Sheet - Rev 2.0
09/2003
AWT921
5
PERFORMANCE DATA
30
32
34
36
38
40
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
Pin (dBm)
Pout
(dBm)
0
20
40
60
80
100
PAE
(%)
Pout
PAE
Figure 3: Output Power and Power Added
Efficiency vs. Pin
Figure 4: Output Power and Power Added
Efficiency vs. Frequency
35
36
37
38
39
40
41
42
43
920
925
930
935
940
945
950
955
960
Freq (MHz)
Pout
(dBm)
0
10
20
30
40
50
60
Pout
PAE
Figure 5: Output Power and PAE vs.
Supply Voltage
35
36
37
38
39
40
41
5
6
7
8
9
10
11
Supply Voltage (V)
Pout
(dBm)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
PAE
(
%)
Pout
PAE
Vds1=Vds2=Vds3
Figure 6: Third Stage Quiescent Current vs.
Reference Voltage with Various R
REF
0
100
200
300
400
500
600
700
0
1
2
3
4
5
6
7
8
9
Vref (V)
Pout
(dBm)
Rref=1.5KOhms
Rref=3KOhms
Rref=6KOhms
Idq3
(mA)
Figure 7: Third Stage Quiescent Current
vs. V , R
= 1.8 K
DD
REF
W
0
50
100
150
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Vdd (V)
Idq3
(mA)
Idq3
Figure 8: Third Stage Quiescent Current
vs. V , R
= 1.8 K
SS
REF
W
0
50
100
150
200
250
300
350
400
450
500
-7
-6
-5
-4
-3
-2
-1
Vss (V)
Idq3
(mA)
Idq3
6
Data Sheet - Rev 2.0
09/2003
AWT921
Figure 9: Small Signal Gain, Saturated Power,
and Efficiency vs. Temperature
28
30
32
34
36
38
40
-30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature (C)
P
o
u
t
(d
B
m
),
G
a
in
(d
B
)
0
10
20
30
40
50
60
PA
E
(
%
)
Pout
SS Gain
PAE
Figure 10: Third Stage Quiescent Current,
Reference Current vs. Temperature
0
50
100
150
200
250
300
350
400
450
-30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature (C)
Iq3
(
mA)
0
0.5
1
1.5
2
2.5
3
Iref
(mA)
Iq3
Iref
Figure 11: Test Circuit Impedance Presented to
the First Stage Drain (Vd1)
MARKER 1
0.926500000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 -
2.000000000 GHz
S11 FORWARD REFLECTION
IMPEDANCE
CH 1
- S11
REFERENCE PLANE
16.2900 cm
0.959750000 GHz
8.126
9.834
114.075 j
126.385 j
2
1
2
Figure 12: Test Circuit Impedance Presented to
the Second Stage Drain (Vd2)
MARKER 1
0.926500000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 -
2.000000000 GHz
S11 FORWARD REFLECTION
IMPEDANCE
CH 1
- S11
REFERENCE PLANE
16.2900 cm
0.959750000 GHz
16.486
19.628
181.822 j
205.440 j
2
1
2
Figure 13: Test Circuit Impedance Presented to
the Third Stage Drain (Vd3)
MARKER 1
0.926500000 GHz
MARKER TO MAX
MARKER TO MIN
MARKER READOUT
FUNCTIONS
0
.2
.5
1
2
5
.2
-.2
.5
-.5
1
-1
2
-2
5
-5
0.100000000 -
2.000000000 GHz
S11 FORWARD REFLECTION
IMPEDANCE
CH 1
- S11
REFERENCE PLANE
16.2900 cm
0.959750000 GHz
3.233
3.045
-1.131 j
-344.163 jm
2
1
2
Data Sheet - Rev 2.0
09/2003
AWT921
7
APPLICATION INFORMATION
Figure 14: Application Circuit Schematic
12
16
2
17
6
23
5
15
3
13
22
7
4
28
11
8
20
21
24
25
18
19
10
9
1
14
SL
U
G
C1
F2
C5
L3
F1
C6
C7
C8
R
REF
C9
C10
C11
C12
R2
R1
R4
L1
F3
F4
C13
C15
C16
C17
C19
V
D3
V
D1
V
D2
V
DD
/V
REF
V
SS
GND
RF
IN
RF
OUT
V
G3
AWT921S11
V
D2
V
D1
RF
IN
GND
V
REF
V
DD
V
SS
V
D3
V
G1
V
G2
GND
V
G3
L2
C14
C4
Table 5: Application Circuit Component Values
(925-960 MHz GSM Application)
N
O
I
T
A
N
G
I
S
E
D
E
U
L
A
V
N
O
I
T
A
N
G
I
S
E
D
E
U
L
A
V
1
R
0
0
5
7
1
1
C
,
0
1
C
F
p
0
0
7
2
2
R
K
2
.
2
3
1
C
F
p
1
1
R
F
E
R
K
8
.
1
4
1
C
F
p
0
0
7
4
6
1
C
,
5
C
,
1
C
F
2
.
2
1
L
T
3
0
A
,t
f
a
r
c
il
o
C
H
n
8
9
1
C
,
5
1
C
,
4
C
F
p
3
3
2
L
H
n
2
1
7
1
C
,
6
C
F
p
7
4
3
L
H
n
6
2
1
C
,
9
C
,
8
C
,
7
C
F
1
0
.
0
,
4
F
,
3
F
,
2
F
,
1
F
7
4
e
ti
r
r
e
F
0
0
1
@
o
y
i
a
T
g
n
it
a
R
A
1
,
z
H
M
0
7
4
S
H
5
2
1
2
K
B
,
n
e
d
u
Y
8
Data Sheet - Rev 2.0
09/2003
AWT921
PACKAGE OUTLINE
Figure 15: S11 Package Outline - 28 Pin SSOP 28 Thermal Slug Package
Figure 16: Branding Specification
Data Sheet - Rev 2.0
09/2003
AWT921
9
COMPONENT PACKAGING
Figure 17: Tape & Reel Drawing
Table 6: Tape & Reel Dimensions
E
P
Y
T
E
G
A
K
C
A
P
H
T
D
I
W
E
P
A
T
H
C
T
I
P
T
E
K
C
O
P
Y
T
I
C
A
P
A
C
L
E
E
R
A
I
D
L
E
E
R
X
A
M
E
D
I
W
8
2
-
P
O
S
S
Y
D
O
B
S
E
H
C
N
I
0
3
6
.
0
S
E
H
C
N
I
2
7
4
.
0
0
0
5
3
S
E
H
C
N
I
3
1
10
Data Sheet - Rev 2.0
09/2003
AWT921
NOTES
Data Sheet - Rev 2.0
09/2003
AWT921
11
NOTES
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
Data Sheet - Rev 2.0
09/2003
12
AWT921
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