Anadigm
UM020800-U005
AN10E40
Field Programmable Analog Array
The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit
realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched
capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are
directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up
via an off chip serial PROM or through the AN10E40s standard microprocessor peripheral interface.
A configuration memory image is easily constructed using the companion AnadigmDesigner software which
includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often
consumed one at a time, though some of the more complex library functions may consume two or more blocks.
Specialized IO cells surround the core to bring your analog signals in and out of the array.
The AN10E40 coupled with the intuitive AnadigmDesigner software gives both digital and analog designers a
competitive advantage in designing analog circuits that cant really be compared to any other design system in
existence. Quickly constructed, accurate, drift free, temperature compensated and programmable analog circuits
are now yours. Imagine the power of programmable with the versatility of analog.
Benefits
Extremely Rapid Analog Design Minutes not weeks to re-spin a new design idea
In Circuit Programmable Behavior can be changed as fast as 125 microseconds
Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers
Extremely Stable over Voltage and Temperature
No Component Aging
Reliable and Repeatable Performance
Flexible Internal Clock and Routing Resources
No More Trimming Components
No More Tuning Components
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Config. Logic
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Configuration Data Shift Register
Anadigm
UM020800-U005
Anadigm reserves the right to make any changes without further notice to any
products herein. Anadigm makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does
Anadigm assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including with limitation
consequential or incidental damages. Typical parameters can and do vary in
different applications. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts.
Anadigm does not convey any license under its patent rights nor the rights of
others. Anadigm products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Anadigm product could create a situation where personal injury
or death may occur. Should buyer purchase or use Anadigm product for any
such unintended or unauthorized application, buyer shall indemnify and hold
Anadigm and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim
alleges that Anadigm was negligent regarding the design or manufacture of the
part.
Copyright Anadigm 2002
All Rights Reserved
AN10E40 Data Manual
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Table of Contents
Features of AN10E40 ...................................................................................................................................................... 1
Available IPmodule Functions ......................................................................................................................................... 1
How It Works .................................................................................................................................................................... 1
AN10E40 Architecture ..................................................................................................................................................... 2
The Configurable Analog Block....................................................................................................................................... 3
A Quick Review of Switched Capacitor Circuits ......................................................................................................... 3
CAB Details .................................................................................................................................................................. 4
Routing Resources........................................................................................................................................................... 4
Clock Generation ............................................................................................................................................................. 4
Voltage Reference ........................................................................................................................................................... 5
Voltage Mid-Rail Generator ............................................................................................................................................. 5
Analog Input Output Cell.................................................................................................................................................. 6
Sallen Key Filtering ...................................................................................................................................................... 6
2
nd
Order Sallen-Key Filter for Output Smoothing ...................................................................................................... 7
4
th
Order Sallen-Key Filter for Output Smoothing ....................................................................................................... 7
2
nd
Order Sallen-Key Filter for Input Anti-Aliasing ...................................................................................................... 7
4
th
Order Sallen-Key Filter for Input Anti-Aliasing ....................................................................................................... 8
Configuration Engine ....................................................................................................................................................... 9
Mode 0 Micro Mode (Parallel Loading) .................................................................................................................. 10
Micro Mode Maximum Data Transfer Rate ........................................................................................................... 12
Function Register (RS=0) and Data/Status Register (RS=1) ............................................................................... 12
Sending the Reset Device Command ................................................................................................................... 12
Micro Mode - Configuration Sequence .................................................................................................................. 13
Organization of Configuration Memory - The ASCII Hex Configuration File Format .......................................... 14
Mode 1 Boot from ROM (BFR Mode)..................................................................................................................... 15
BFR Timing................................................................................................................................................................. 16
Configuration Clock .................................................................................................................................................... 17
Reset Sequences........................................................................................................................................................... 18
Analog Power On Reset (APOR) & Power On Reset (POR) ................................................................................... 18
Internal Reset Activity................................................................................................................................................. 18
External Reset Assertion............................................................................................................................................ 18
Mechanical ..................................................................................................................................................................... 18
Package Details.......................................................................................................................................................... 18
Pin Out Description .................................................................................................................................................... 19
Package Pin Electrical Characterization ................................................................................................................... 22
Powers, Grounds and Bypassing .................................................................................................................................. 22
Recommended Configuration for Power & Ground .................................................................................................. 22
AVDD and AVSS ........................................................................................................................................................ 22
SVDD and SVSS ........................................................................................................................................................ 22
BVDD and BVSS ........................................................................................................................................................ 23
ESD_VDD and ESD_VSS ......................................................................................................................................... 23
CFG_VDD and CFG_VSS ......................................................................................................................................... 23
OPAMVMR and CEXT ............................................................................................................................................... 23
The AN10E40 in Split Supply Systems ..................................................................................................................... 23
Characterized Electrical Parameters............................................................................................................................. 24
Absolute Maximum Ratings ....................................................................................................................................... 24
Recommended Operating Conditions ....................................................................................................................... 24
Power Consumption ................................................................................................................................................... 24
Digital Interface Characteristics ................................................................................................................................. 25
VMR (Voltage Mid-Rail) ............................................................................................................................................. 25
Vref (Reference Voltage) ........................................................................................................................................... 26
Analog Input/Output Buffer ........................................................................................................................................ 26
I/O Cell Bandwidth (Unity gain buffer) ....................................................................................................................... 27
I/O Buffer Cell Configured as a Sallen-Key Filter ..................................................................................................... 27
Analog Core Cell (C.A.B. Configurable Analog Block) Amplifier.............................................................................. 28
Typical Performance Examples..................................................................................................................................... 29
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Anadigm
UM020800-U005
A Programmable Inverting Gain Stage ......................................................................................................................29
A Programmable Low Pass Filter...............................................................................................................................29
Sine Wave Oscillator ..................................................................................................................................................30
Electrostatic Discharge Characterization ......................................................................................................................31
A Quick Review of ESD Basics..................................................................................................................................31
Catastrophic Failure................................................................................................................................................31
Latent Defect ...........................................................................................................................................................31
Basic ESD Events--What Causes Electronic Devices to Fail? .............................................................................31
Discharge to the Device..........................................................................................................................................31
Discharge from the Device .....................................................................................................................................31
Field Induced Discharges .......................................................................................................................................31
AN10E40 ESD Classifications ...................................................................................................................................32
Standard ESD Classifications ................................................................................................................................32
AN10E40 Data Manual
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Anadigm
UM020800-U005
Features of AN10E40
20 Programmable Analog Cells
13 Analog IO Cells
2 Spare Op-Amps
8 Bit Programmable Internal Vref Source
4 Programmable Internal Clock Sources
Easy Power-On-Reset Self Boot Using Serial PROM
Microprocessor Boot Option
Intuitive Design Software
Drift Free Designs
Rapidly
Configurable
Available IPmodule Functions
Gain
Stages
Summing
Amplifiers
Sample and Hold
Track and Hold
High, Low and Band Pass/Stop Filters
High Q, Low Q Filters
Cosine
Filters
Full and Half Non/Inverting Rectifiers
Non/Inverting
Comparators
1 and 2 Input Comparators
DC Reference Voltage Sources
Limiters
Schmitt
Triggers
Non/Inverting
Integrators
Differentiators
New IP Modules Continuously Available
How It Works
On power up, the AN10E40s reset circuitry initializes the configuration engine. The configuration engine takes over
and first examines the state of the Mode port. The pin settings of the Mode port determine which of the boot
methods should be exercised. One popular option is to boot from an off chip Serial PROM. The configuration
engine takes care of taking data out of the Serial PROM and loading it into on-chip configuration SRAM. The whole
boot process takes just a few milliseconds. Once the configuration SRAM has been loaded, the analog circuitry is
automatically enabled and the configuration engine idled. The chip now performs the analog functions according to
the configuration bit stream just loaded.
Creating a configuration bit stream is no more complicated than using the device itself. The AnadigmDesigner
design tool provides the user an intuitive drag and drop GUI in which you simply select several of the IPmodule
functions from the extensive library, drop them onto a graphical representation of the chip, fill in some parametric
information about the IPmodule, wire up the internal and I/O connections, and hit a button to generate the bit
stream (or download it directly to the device on your bench).
The device internals are more complicated than the easy to use device may lead you to believe. The AN10E40
array is based on programmable switched capacitor op-amp cells with very flexible internal and external connection
and clocking resources. The AnadigmDesigner and the associated IPmodule library shields the user from these
complexities.
Switched capacitor circuits are remarkably stable over voltage, temperature and device aging. Using the AN10E40
for your analog circuit realization allows you to rest assured knowing that once a circuit has been designed, it will
continue perform as expected. Say goodbye to trim pots.
Another advantage of this technology is the tremendous decrease in design time. Along with the elimination of trim
pots, youll also be able to clear your bench of all the normal discrete R and C components. Prototyping is now a
drag and drop computer exercise. A simple push of a button and your design is downloaded into the AN10E40
nearly instantaneously.
The kicker to all of this is that it is infinitely re-programmable. If a single set of analog functions is not sufficient for
your system, then you can load new configuration files into the AN10E40 with only a very small interruption to the
analog signal stream. Consider how filter parameters can be changed to adapt to varying input signal conditions.
Consider how a single physical circuit can be used in all of your different system designs. Consider all the
advantages that programmable analog will bring to your designs.
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