ChipFind - документация

Электронный компонент: AOU412

Скачать:  PDF   ZIP
Symbol
V
DS
V
GS
I
DM
I
AR
E
AR
T
J
, T
STG
Symbol
Typ
Max
R
JA
105
125
R
JL
1
1.5
T
C
=100C
I
D
85
65
W
Junction and Storage Temperature Range
A
P
D
C
100
50
-55 to 175
120
mJ
Continuous Drain
Current
B,G
Maximum
Units
Parameter
T
C
=25C
G
T
C
=100C
B
30
200
Avalanche Current
C
30
Pulsed Drain Current
Power Dissipation
B
T
C
=25C
Gate-Source Voltage
Absolute Maximum Ratings T
A
=25C unless otherwise noted
V
V
20
Drain-Source Voltage
A
Repetitive avalanche energy L=0.1mH
C
Maximum Junction-to-Lead
C
Steady-State
C/W
Thermal Characteristics
Parameter
Units
C/W
Maximum Junction-to-Ambient
A
Steady-State
AOU412
N-Channel Enhancement Mode Field Effect Transistor
Features
V
DS
(V) = 30V
I
D
= 85A (V
GS
= 10V)
R
DS(ON)
< 7.5m
(V
GS
= 10V)
R
DS(ON)
< 11m
(V
GS
= 4.5V)
General Description
The AOU412 uses advanced trench technology to
provide excellent R
DS(ON)
, low gate chargeand low
gate resistance. This device is ideally suited for use
as a high side switch in CPU core power conversion.
Standard Product AOU412 is Pb-free (meets ROHS
& Sony 259 specifications). AOU412L is a Green
Product ordering option. AOU412 and AOU412L are
electrically identical.
G
D
S
Top View
Drain
Connected to
Tab
TO-251
G D S
Alpha & Omega Semiconductor, Ltd.
AOU412
Symbol
Min
Typ
Max
Units
BV
DSS
30
V
0.005
1
T
J
=55C
5
I
GSS
100
nA
V
GS(th)
1.5
2.15
2.5
V
I
D(ON)
85
A
5.7
7.5
T
J
=125C
8.4
10
8.7
11
m
g
FS
60
S
V
SD
0.72
1
V
I
S
85
A
C
iss
1320
1600
pF
C
oss
533
pF
C
rss
154
pF
R
g
0.95
1.2
Q
g
(10V)
26
32
nC
Q
g
(4.5V)
13.3
16.2
nC
Q
gs
3.2
nC
Q
gd
6.6
nC
t
D(on)
7.2
10
ns
t
r
12.5
18
ns
t
D(off)
22
33
ns
t
f
6
9
ns
t
rr
29.7
36
ns
Q
rr
29
36
nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge I
F
=20A, dI/dt=100A/
s
Drain-Source Breakdown Voltage
On state drain current
I
D
=250
A, V
GS
=0V
V
GS
=10V, V
DS
=5V
V
GS
=10V, I
D
=20A
Reverse Transfer Capacitance
I
F
=20A, dI/dt=100A/
s
Electrical Characteristics (T
J
=25C unless otherwise noted)
STATIC PARAMETERS
Parameter
Conditions
I
DSS
A
Gate Threshold Voltage
V
DS
=V
GS
I
D
=250
A
V
DS
=24V, V
GS
=0V
V
DS
=0V, V
GS
= 20V
Zero Gate Voltage Drain Current
Gate-Body leakage current
R
DS(ON)
Static Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Maximum Body-Diode Continuous Current
Input Capacitance
Output Capacitance
DYNAMIC PARAMETERS
m
V
GS
=4.5V, I
D
=20A
I
S
=1A,V
GS
=0V
V
DS
=5V, I
D
=20A
Turn-On Rise Time
Turn-Off DelayTime
V
GS
=10V, V
DS
=15V, R
L
=0.75
,
R
GEN
=3
Turn-Off Fall Time
Turn-On DelayTime
Gate Drain Charge
V
GS
=0V, V
DS
=15V, f=1MHz
SWITCHING PARAMETERS
Total Gate Charge
Gate Source Charge
Gate resistance
V
GS
=0V, V
DS
=0V, f=1MHz
V
GS
=4.5V, V
DS
=15V, I
D
=20A
Total Gate Charge
A: The value of R
JA
is measured with the device in a still air environment with T
A
=25C.
B. The power dissipation P
D
is based on T
J(MAX)
=175C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature T
J(MAX)
=175C.
D. The R
JA
is the sum of the thermal impedence from junction to case R
JC
and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300
s pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of T
J(MAX)
=175C.
G. The maximum current rating is limited by bond-wires.
Rev3: August 2005
Alpha & Omega Semiconductor, Ltd.
AOU412
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
0
10
20
30
40
50
60
0
1
2
3
4
5
V
DS
(Volts)
Fig 1: On-Region Characteristics
I
D
(A
)
V
GS
=3V
3.5V
10V
4.0V
0
10
20
30
40
50
60
1.5
2
2.5
3
3.5
4
4.5
V
GS
(Volts)
Figure 2: Transfer Characteristics
I
D
(A
)
4
5
6
7
8
9
10
11
12
0
10
20
30
40
50
60
I
D
(A)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage
R
DS
(
O
N)
(m
)
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
SD
(Volts)
Figure 6: Body-Diode Characteristics
I
S
(A
)
25C
125C
0.8
1
1.2
1.4
1.6
1.8
0
25
50
75
100
125
150
175
Temperature (C)
Figure 4: On-Resistance vs. Junction
Temperature
N
o
r
m
a
lized
On
-
R
esist
a
n
c
e
V
GS
=10V
V
GS
=4.5V
4
8
12
16
20
2
4
6
8
10
V
GS
(Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
R
DS
(
O
N)
(m
)
25C
125C
V
DS
=5V
V
GS
=4.5V
V
GS
=10V
I
D
=20A
25C
125C
I
D
=20A
Alpha & Omega Semiconductor, Ltd.
AOU412
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
0
2
4
6
8
10
0
5
10
15
20
25
30
Q
g
(nC)
Figure 7: Gate-Charge Characteristics
V
GS
(V
ol
ts)
0
400
800
1200
1600
2000
2400
0
5
10
15
20
25
30
V
DS
(Volts)
Figure 8: Capacitance Characteristics
C
a
p
acitan
ce (p
F
)
C
iss
0
200
400
600
800
1000
1E-05 1E-04 0.001 0.01
0.1
1
10
100
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note F)
Po
w
e
r (
W
)
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
1
10
100
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Z
JC
N
o
r
m
a
liz
ed
T
r
an
sien
t
T
h
er
m
al R
esistan
ce
C
oss
C
rss
0.1
1
10
100
1000
0.1
1
10
100
V
DS
(Volts)
I
D
(A
m
p
s)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
100
s
10ms
1ms
DC
R
DS(ON)
limited
T
J(Max)
=175C
T
A
=25C
V
DS
=15V
I
D
=20A
Single Pulse
D=T
on
/T
T
J,PK
=T
A
+P
DM
.Z
JC
.R
JA
R
JC
=1.5C/W
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, single pulse
T
J(Max)
=175C
T
A
=25C
10
s
Alpha & Omega Semiconductor, Ltd.
AOU412
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
0
20
40
60
80
100
120
0.00001
0.0001
0.001
0.01
Time in avalanche, t
A
(s)
Figure 12: Single Pulse Avalanche capability
I
D
(A
), P
eak A
valan
ch
e C
u
r
r
en
t
0
20
40
60
80
100
120
0
25
50
75
100
125
150
175
T
CASE
(C)
Figure 13: Power De-rating (Note B)
P
o
w
e
r
D
i
s
s
i
pa
ti
on (W
)
T
A
=25C
DD
D
A
V
BV
I
L
t
-
=
0
20
40
60
80
100
0
25
50
75
100
125
150
175
T
CASE
(C)
Figure 14: Current De-rating (Note B)
C
u
rre
n
t
ra
t
i
n
g
I
D
(A
)
Alpha & Omega Semiconductor, Ltd.