Document Outline

• ARM1020E
  • Change history
  • Contents
  • List of Tables
  • List of Figures
  • Preface
    • About this document
      • Key to timing diagram conventions
      • Register notation conventions
    • Feedback
  • Introduction
    • 1.1 About the processor
    • 1.2 Components of the processor
      • Figure11 ARM1020E processor block diagram
    • 1.3 Silicon revision information
  • Integer Core
    • 2.1 About the integer core
      • Integer core
    • 2.2 Pipeline
    • 2.3 Prefetch unit
    • 2.4 Typical operations
      • Figure22 Pipeline stages of a typical operation
      • Figure23 Pipeline stages of a typical ALU operation
      • Figure24 Pipeline stages of a typical multiply operation
    • 2.5 Load/store unit
    • 2.6 Instruction progression
      • Figure25 Pipeline stages of a load or store operation
      • Figure26 Pipeline stages of a load multiple or store multiple operation
      • Figure27 Pipeline stages of an LDR operation that misses
  • Programmer�s Model
    • 3.1 About the programmer�s model
    • 3.2 Instruction set summary
      • Table31 Key to instruction set table notation
        • Table32 ARM instruction summary
        • Table33 Addressing mode 2
        • Table34 Addressing mode 2, privileged
        • Table35 Addressing mode 3
        • Table36 Addressing mode 4, load
        • Table37 Addressing mode 4, store
        • Table38 Addressing mode 5
        • Table39 Oprnd2 examples
        • Table310 Suffixes to set fields
        • Table311 Condition fields
        • Table312 Thumb instruction summary
  • System Control Coprocessor
    • 4.1 About the system control coprocessor
      • Figure41 CP15 MCR instruction format
      • Figure42 CP15 MRC instruction format
      • Table41 CP15 register summary
      • Table42 Address types
    • 4.2 Register descriptions
      • Table43 Device ID and Cache Type Register instructions
        • Figure43 Device ID Register
        • Table44 Encoding of the Device ID Register
        • Figure44 Cache Type Register
        • Table45 Encoding of the Cache Type Register
      • Table46 Control Register 1 instructions
      • Figure45 Control Register 1
      • Table47 Encoding of Control Register 1
      • Table48 Translation Table Base Register instructions
      • Figure46 Translation Table Base Register
      • Table49 Domain Access Control Register instructions
      • Figure47 Domain Access Control Register
      • Table410 Encoding of the Domain Access Control Register
        • Table411 Data Fault Status Register instructions
        • Figure48 Data Fault Status Register
        • Table412 Encoding of the Data Fault Status Register 
        • Table413 Priority of data fault types
        • Table414 Instruction Fault Status Register instructions
        • Figure49 Instruction Fault Status Register
        • Table415 Encoding of the Instruction Fault Status Register 
      • Table416 Fault Address Register instructions
      • Figure410 Fault Address Register
      • Table417 Cache Operations Register instructions 
      • Table418 Cache operation descriptions
        • Figure411 Index Cache Operations Register
        • Table419 Encoding of the Index Cache Operations Register
        • Figure412 VA Cache Operations Register
        • Table420 Encoding of the VA Cache Operations Register
      • Table421 TLB Operations Register instructions
      • Figure413 TLB Operations Register
      • Table422 Cache Lockdown Register instructions
      • Figure414 Cache Lockdown Register
      • Table423 TLB Lockdown Register instructions
      • Figure415 TLB Lockdown Register
      • Table424 Process ID and Context ID Register instructions
      • Figure416 Process ID Register
      • Figure417 Context ID Register
        • Figure418 Address mapping using CP15 R13
        • Table425 PLL Configuration Register instructions
        • Figure419 PLL Configuration Register
        • Table426 Encoding of the PLL Configuration Register 
        • Table427 Power Manager Status instructions
        • Figure420 Power Manager Status Register
        • Table428 Encoding of the Power Manager Status Register
        • Figure421 Power Manager Receive Data Register
        • Table429 Encoding of the Power Manager Receive Data Register
        • Figure422 Power Manager Transmit Data Register
        • Table430 Encoding of the Power Manager Transmit Data Register
        • Table431 Control Register 2 instructions
        • Figure423 Control Register 2
        • Table432 Encoding of Control Register 2
  • Memory Management Units
    • 5.1 About the MMUs
    • 5.2 MMU software-accessible registers
      • Table51 CP15 register MMU functions
    • 5.3 Address translation
      • Figure51 Address translation overview
      • Figure52 Translating a level 1 descriptor address
      • Figure53 Level 1 descriptor formats
      • Table52 Access types in a level 1 descriptor
        • Figure54 Translating a section address
      • Figure55 Level 2 descriptor formats
        • Figure56 Translating a coarse page table address
        • Table53 Access types in a coarse page table descriptor
        • Figure57 Translating a large page or subpage address from a coarse page table
        • Figure58 Translating a small page or subpage address from a coarse page table
        • Figure59 Translating a fine page table address
        • Table54 Access types in a fine page table descriptor
        • Figure510 Translating a large page or subpage address from a fine page table
        • Figure511 Translating a small page or subpage address from a fine page table
        • Figure512 Translating a tiny page address
    • 5.4 MMU memory access control
      • Table55 Domain access encoding
      • Table56 S and R bit encoding
    • 5.5 MMU cachable and bufferable information
      • Table57 C and B bit access control
    • 5.6 MMU and write buffer
    • 5.7 MMU aborts
    • 5.8 MMU fault checking sequence
      • Figure513 Fault checking flowchart
    • 5.9 CPU aborts on MMU faults
    • 5.10 Fault priority
      • Table58 Priority encoding of MMU faults
    • 5.11 External aborts
      • Table59 First-access-only external abort
      • Table510 First-access and page-boundary external aborts
      • Table511 First-access and last-access external aborts
    • 5.12 Interaction of the MMU, caches, and write buffer
    • 5.13 Soft page table support
      • Figure514 Instruction TLB bit fields
      • Table512 Encoding of instruction TLB bit fields
      • Figure515 Protected RAM bit fields
      • Table513 Protected RAM bit field values
      • Figure516 Physical address RAM bit fields
      • Table514 TLB physical address bit fields and meanings
  • Caches and Write Buffer
    • 6.1 About the caches and write buffer
    • 6.2 ICache
      • Table61 Selection of cachable instructions
    • 6.3 DCache and write buffer
      • Table62 Selection of cachable and bufferable data
    • 6.4 Cache coherence
    • 6.5 Portability issues
  • Prefetch Unit
    • 7.1 About the prefetch unit
    • 7.2 Branch prediction activity
      • Table71 Penalty for an erroneously predicted branch
    • 7.3 Branch instruction cycle summary
      • Table72 ARM and Thumb branch instruction cycle counts
    • 7.4 Instruction memory barriers
  • Bus Interface
    • 8.1 Bus features
    • 8.2 AMBA AHB signals
      • Table81 AMBA AHB signals
    • 8.3 Arbiter signals
      • Table82 Arbiter signals
        • Figure81 Arbiter-bus interface connections
    • 8.4 AHB control signals
      • Table83 Transfer sizes
      • Table84 BURST lengths
      • Table85 Transfer attributes
    • 8.5 Timing
    • 8.6 Bus interface
      • Table86 Blocking and nonblocking request types
      • Table87 Typical bus interface request sizes
        • Figure82 Bus interface block diagram
        • Figure83 Write buffer and castout buffer
          • Table88 Cachable and bufferable bits in buffered writes
  • Coprocessor Interface
    • 9.1 About the coprocessor interface
      • Figure91 ARM10 and CP pipeline stages
    • 9.2 Coprocessor interface signals
    • 9.3 Design considerations
      • Figure92 ARM10 coprocessor inputs
    • 9.4 Parallel execution
    • 9.5 Rules for the interface
    • 9.6 Pipeline signal assertion
      • Table91 Pipeline stages and active signals
    • 9.7 Instruction issue
      • Table92 CPINSTR interactions with other signals
      • Table93 CPINSTRV interactions with other signals
      • Table94 CPVALIDD interactions with other signals
      • Figure93 Instruction issue example
        • Table95 CPLSLEN interactions with other signals
        • Table96 CPLSSWP interactions with other signals
        • Table97 CPLSDBL interactions with other signals
    • 9.8 Hold signals
      • Table98 Hold signals summary
        • Table99 ASTOPCPD interactions with other signals
        • Figure94 ASTOPCPD example
        • Table910 ASTOPCPE interactions with other signals
        • Figure95 ASTOPCPE example
        • Table911 LSHOLDCPE interactions with other signals
        • Figure96 LSHOLDCPE example
        • Table912 LSHOLDCPM interactions with other signals
        • Figure97 LSHOLDCPM example
        • Table913 CPBUSYE interactions with other signals
        • Figure98 CPBUSYE example
        • Figure99 CPBUSYE ignored due to ASTOPCPD assertion
        • Figure910 CPBUSYE asserted before ASTOPCPD
        • Figure911 ASTOPCPD with CPBUSYE
        • Figure912 CPBUSYE ignored due to ASTOPCPE assertion
        • Figure913 CPBUSYE asserted before ASTOPCPE
        • Figure914 I2 held up by ASTOPCPE and CPBUSYE
        • Figure915 I1 held up by ASTOPCPE and I2 held up by CPBUSYE
        • Figure916 I1 held up by CPBUSYE and I2 held up by ASTOPCPD
        • Table914 CPLSBUSY interactions with other signals
    • 9.9 Instruction cancelation
      • Table915 ACANCELCP interactions with other signals
      • Figure917 ACANCELCP example
      • Figure918 ACANCELCP with ASTOPCPE example
      • Figure919 ACANCELCP with CPBUSYE example
      • Table916 AFLUSHCP interactions with other signals
      • Figure920 AFLUSHCP example
    • 9.10 Bounced instructions
      • Table917 CPBOUNCEE interactions with other signals
      • Figure921 CPBOUNCEE example
      • Figure922 CPBOUNCEE with ASTOPCPE example
      • Figure923 CPBOUNCEE with CPBUSYE example
    • 9.11 Data buses
      • Table918 STCMRCDATA interactions with signals
      • Table919 LDCMRCDATA interactions with signals
  • JTAG Interface
    • 10.1 JTAG interface and halt mode
      • Figure101 JTAG TAP state machine diagram
    • 10.2 JTAG instructions
      • Table101 Defined public JTAG instructions
    • 10.3 Scan chain descriptions
      • Figure102 TAP ID Register
      • Table102 Method of debug entry bit values
      • Table103 DSCR bits from the core
      • Figure103 Scan chain 2
  • Debug
    • 11.1 About the debug unit
      • Table111 CP14 registers and scan chain numbers
    • 11.2 Register descriptions
      • Table112 Debug ID Register instructions
      • Figure111 Debug ID Register
      • Table113 Encoding of the Debug ID Register
      • Table114 Debug Status and Control Register instructions
      • Figure112 Debug Status and Control Register
      • Table115 Encoding of Debug Status and Control Register
      • Table116 Data Transfer Register instructions
      • Figure113 Data Transfer Register
      • Table117 Breakpoint Address Register instructions
      • Figure114 Breakpoint Address Registers
      • Table118 Breakpoint Control Register instructions
      • Figure115 Breakpoint Control Registers
      • Table119 Encoding of Breakpoint Control Registers
      • Table1110 Watchpoint Address Register instructions
      • Figure116 Watchpoint Address Registers
      • Table1111 Watchpoint Control Register instructions
      • Figure117 Watchpoint Control Registers
      • Table1112 Encoding of Watchpoint Control Registers
    • 11.3 Software lockout function
    • 11.4 Halt mode
    • 11.5 Monitor mode
    • 11.6 Values in the Link Register after aborts
      • Table1113 Values in the Link Register after exceptions
      • Table1114 Value in the Link Register after a watchpoint
    • 11.7 Comms channel
      • Figure118 Comms channel output
  • Instruction Cycle Summary and Interlocks
    • 12.1 Cycle timing considerations
    • 12.2 Instruction cycle counts
      • Table121 Subcategories of data processing instructions
      • Table122 Cycle counts of data processing instructions 
      • Table123 Cycle counts of multiply instructions
      • Table124 Cycle counts of branch instructions
      • Table125 Cycle counts of MRS and MSR instructions
      • Table126 Cycle counts of load instructions
      • Table127 Cycle counts of store instructions
      • Table128 Cycle counts of load multiple and store multiple instructions
      • Table129 Cycle counts of preload instructions
      • Table1210 Cycle counts of coprocessor instructions 
      • Table1211 Cycle counts of swap instructions
      • Table1212 Cycle counts of Thumb data processing instructions
      • Table1213 Cycle count of the Thumb multiply instruction
      • Table1214 Cycle counts of Thumb branch instructions
      • Table1215 Cycle counts of Thumb store instruction
      • Table1216 Cycle counts of Thumb load instructions
      • Table1217 Cycle counts of Thumb load/store multiple instructions
    • 12.3 Interlocks
      • Figure121 Pipeline forwarding paths
  • Design for Test
    • 13.1 Test modes and ports
      • Table131 ATPG mode selection
      • Table132 Test port signals
      • Table133 Cache upload signal constraints
      • Table134 Test port wrapper signals
    • 13.2 Scan chain configuration
      • Table135 Scan chain configurations
      • Table136 Wrapper scan chain concatenations
    • 13.3 Clocks and clock gating
      • Table137 Scan chain clocks
        • Figure131 Production scan mode clocking
        • Figure132 Clocking in serial core test mode
    • 13.4 Wrapper cells
      • Figure133 Dedicated input and output wrapper cells
      • Figure134 Reset dedicated wrapper cell
      • Figure135 HRESET and SFRESET wrapper cell
      • Figure136 Shared wrapper cells
      • Figure137 HCLK domain wrapper chain isolation
    • 13.5 Reset
    • 13.6 Memories
      • Table138 Test pin configuration for upload, download, and BIST
      • Table139 Encoding of BIST instruction fields
        • Table1310 Encoding of BIST engine control field
        • Table1311 Encoding of BIST block under test field
        • Table1312 Encoding of BIST data word field
        • Table1313 Encoding of BIST pattern field
        • Table1314 BIST pattern terms and definitions
      • Table1315 A1020SCANOUT[15:0] mapping
      • Table1316 Failure address formulas
    • 13.7 Memory BIST waveforms
      • Figure138 Reset followed by BIST test
      • Table1317 Instruction fields for reset followed by BIST test
      • Figure139 Test completion followed by a new test
      • Table1318 Instruction fields for test completion followed by new test
      • Figure1310 Setting a real time failure flag
      • Figure1311 Completion of pattern fail test
    • 13.8 Cache upload/download, manufacturing test
      • Figure1312 Cache upload test execution
      • Table1319 Instruction fields for cache download
      • Figure1313 Execution of cache download start
      • Figure1314 Execution of binary test download
    • 13.9 Test signal value tables
      • Table1320 Test signals for ATPG testing
      • Table1321 Test signals in functional mode
      • Table1322 Test signals during BIST testing
      • Table1323 Test signals in cache upload mode
      • Table1324 Test signals in external test wrapper mode with one wrapper chain
      • Table1325 Test signals in external test wrapper mode with three wrapper chains
  • Power Manager
    • 14.1 About the power manager
    • 14.2 ARM10 processor power modes
      • Table141 ARM10 processor power modes
      • Figure141 Power manager state diagram
      • Table142 Power mode VDD states
        • Table143 Reentering RUN mode
    • 14.3 System control coprocessor
      • Figure142 Power Manager Status Register
      • Table144 PMSR bit fields
      • Figure143 Power Manager Receive Data Register
      • Table145 PMRDR bit fields
      • Figure144 Power Manager Transmit Data Register
      • Table146 PMTDR bit fields
    • 14.4 Programming examples
    • 14.5 Power manager interface
      • Table147 Power manager/processor interface signals
    • 14.6 Timing
      • Figure145 CPU transmit request timing
      • Figure146 CPU transmit request timing with emulation bit set
      • Figure147 CPU previous state request timing
      • Figure148 CPU previous state request timing with emulation bit set
      • Figure149 Hard reset timing
      • Figure1410 Soft reset from power-down timing
    • 14.7 Software example code sequences
  • Clock Generator
    • 15.1 Features
    • 15.2 About the clock generator
      • Figure151 Clock generator block diagram
      • Table151 GCLK/HCLK frequencies with XTAL1=20MHz
    • 15.3 Interface description
      • Table152 Test mode programming
    • 15.4 Output clock behavior
      • Table153 GCLK and HCLK behavior
    • 15.5 PLL Configuration Register
      • Figure152 PLL Configuration Register
    • 15.6 Output clock balancing
      • Figure153 Output clock balancing
  • Signal Descriptions
    • A.1 Global control signals
      • TableA1 Global control signals
    • A.2 AHB signals in normal mode
      • TableA2 AHB signals
      • TableA3 Arbiter signals
    • A.3 PLL signals
      • TableA4 PLL signals
    • A.4 Power manager signals
      • TableA5 Power manager/processor interface signals
    • A.5 JTAG and TAP controller signals
      • TableA6 JTAG signals
      • TableA7 TAP controller signals
    • A.6 Debug signals
      • TableA8 Debug signals
    • A.7 Coprocessor signals
      • TableA9 Coprocessor signals
    • A.8 Design for test signals
      • TableA10 Design for test signals
    • A.9 ETM signals
      • TableA11 ETM10 signals
  • Glossary
  • Index
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