SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE1\, CE2, and OE\
options.
All inputs and outputs are TTL compatible
OPTIONS
MARKING
Timing
12ns access
-12 (contact factory)
15ns access
-15
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
55ns access
-55*
70ns access
-70*
Package(s)
Ceramic DIP (400 mil)
C
No. 111
Ceramic DIP (600 mil)
CW
No. 112
Ceramic LCC
EC
No. 207
Ceramic LCC
ECA
No. 208
Ceramic Flatpack
F
No. 303
Ceramic SOJ
DCJ
No. 501
Ceramic SOJ
SOJ
No. 507
2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-89598
MIL-STD-883
NC
1
32
V
CC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
V
SS
16
17
DQ4
NC
1
32
V
CC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
V
SS
16
17
DQ4
NC
1
32 V
CC
A16
2
31 A15
A14
3
30 CE2
A12
4
29 WE\
A7
5
28 A13
A6
6
27 A8
A5
7
26 A9
A4
8
25 A11
A3
9
24 OE\
A2 10
23 A10
A1 11
22 CE\
A0 12
21 DQ8
DQ1 13
20 DQ7
DQ2 14
19 DQ6
DQ3 15
18 DQ5
V
SS
16
17 DQ4
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat Pack (F)
32-Pin LCC (ECA)
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low power
CMOS designs using a four-transistor memory cell, and are
fabricated using double-layer metal, double-layer polysilicon
technology.
For design flexibility in high-speed memory
applications, this device offers dual chip enables (CE1\, CE2)
and output enable (OE\). These control pins can place the
outputs in High-Z for additional flexibility in system design.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled, allowing system designs to
achieve low standby power requirements.
The "L" version offers a 2V data retention mode, re-
ducing current consumption to 1mA maximum.
128K x 8 SRAM
WITH DUAL CHIP ENABLE
For more products and information
please visit our web site at
www.austinsemiconductor.com
4 3 2 1 32 31 30
A12
A14
A10
NC
V
CC
A15
CE2
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
\
\
\
6
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
ROW DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
GND
DQ8
DQ1
CE1\
CE2
OE\
WE\
A
A
A
A
A
A
A
A
A
COLUMN DECODER
A A A A A A A A
POWER
DOWN
(LSB)
(LSB)
NOTE:
The two least significant row address bits (A8 and A6) are encoded using gray code.
MODE
OE\
CE1\
CE2
WE\
DQ
POWER
STANDBY
X
H
X
X
HIGH-Z
STANDBY
STANDBY
X
X
L
X
HIGH-Z
STANDBY
READ
L
L
H
H
Q
ACTIVE
READ
H
L
H
H
HIGH-Z
ACTIVE
WRITE
X
L
H
L
D
ACTIVE
TRUTH TABLE
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range (Vcc)...............................-.5V to +6.0V
Storage Temperature ....................................-65
C to +150
C
Short Circuit Output Current (per I/O)..........................20mA
Voltage on any Pin Relative to Vss................-.5V to Vcc+1 V
Max Junction Temperature**.......................................+150
C
Power Dissipation .....................................................................1 W
*Stresses at or greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods will affect reliability. Refer to page 17 of this
datasheet for a technical note on this subject.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C & -45
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
CONDITIONS
SYM
MAX
UNITS
NOTES
Input Capacitance (A0-A16)
C
I
12
pF
4
Output Capacitance
C
O
14
pF
4
Input Capacitance (CE\, WE\, OE\)
C
I
20
pF
4
T
A
= 25
o
C, f = 1MHz
V
CC
= 5V
CAPACITANCE
SYM
-12
-15
-20
-25
-35
-45
UNITS NOTES
I
CCSP
250
180
150
140
135
125
mA
3
I
CCLP *
250
180
140
130
125
115
mA
Power Supply
Current: Standby
I
SBT
25
25
25
25
25
25
mA
I
SBC
10
10
10
10
10
10
mA
PARAMETER
Power Supply
Current: Operating
CE\ < V
IL
; OE\, WE\, and CE2>V
IH
V
CC
= MAX, f = MAX = 1/t
RC
(MIN)
Output Open
*L version only
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
-0.2V
V
IH
> V
CC
-0.2V; F = 0 Hz
CE\=V
IH,
CE2=V
IL
; Other Inputs at
<V
IL
, >V
IH
, V
CC
= MAX
f = 0 Hz
MAX
CONDITIONS
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.2
V
CC
+0.5
V
1
Input Low (Logic 0) Voltage
V
IL
-0.5
0.8
V
1, 2
Input Leakage Current
0V<V
IN
<V
CC
IL
I
-10
10
A
Output Leakage Current
Output(s) disabled
0V<V
OUT
<V
CC
IL
O
-10
10
A
Output High Voltage
I
OH
=-4.0mA
V
OH
2.4
V
1
Output Low Voltage
I
OL
=8.0mA
V
OL
0.4
V
1
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C & -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ CYCLE
READ cycle time
t
RC
12
15
20
25
35
45
ns
Address access time
t
AA
12
15
20
25
35
45
ns
Chip Enable access time
t
ACE
12
15
20
25
35
45
ns
Output hold from address change
t
OH
3
3
3
3
3
3
ns
Chip Enable to output in Low-Z
t
LZCE
3
3
3
3
3
3
ns
4, 6, 7
Chip disable to output in High-Z
t
HZCE
7
7
8
10
15
20
ns
4, 6, 7
Output Enable access time
t
AOE
7
7
7
10
15
20
ns
4, 6, 7
Output Enable to output in Low-Z
t
LZOE
0
0
0
0
0
0
ns
Output disable to output in High-Z
t
HZOE
7
7
8
10
15
20
ns
4, 6, 7
WRITE CYCLE
WRITE cycle time
t
WC
12
15
20
25
35
45
ns
Chip Enable to end of write
t
CW
11
12
15
20
25
35
ns
Address valid to end of write
t
AW
11
12
15
20
25
35
ns
Address setup time
t
AS
0
0
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
0
5
ns
WRITE pulse width
t
WP
11
12
15
20
25
35
ns
Data setup time
t
DS
8
8
10
15
20
20
ns
Data hold time
t
DH
0
0
0
0
0
0
ns
Write disable to output in Low-Z
t
LZWE
5
5
5
5
5
5
ns
4, 6, 7
Write Enable to output in High-Z
t
HZWE
7
7
9
10
15
20
ns
4, 6, 7
DESCRIPTION
-20
SYMBOL
-25
-35
-45
-15
-12
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008
Austin Semiconductor, Inc.
MT5C1008
Rev. 6.5 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-2V for pulse width < 20ns
3.
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured 200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The
waveform is inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
+5V
Q
255
30
480
5 pF
+5V
Q
255
480
123
123
123
123
1234
1234
1234
1234
DON'T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
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DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
<V
SS
+ 0.2V
V
IH
V
IL
V
IH
V
IL
V
CC
CE1\
CE2
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
NOTES
V
CC
for Retention Data
V
DR
2
---
V
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V, f=0
V
CC
= 2V
I
CCDR
1.0
mA
Chip Deselect to Data
Retention Time
t
CDR
0
---
ns
4
Operation Recovery Time
t
R
t
RC
ns
4, 11
CONDITIONS
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