ASIX ELECTRONICS CORPORATION
Ver. 0.7
4F, NO.8, Hsin ANN Rd., Science-based Industrial Park, Hsin-Chu City, Taiw
TEL: 886-3-579-9500
X: 886-3-579-9558
http://www.asix.com.tw
AX81190 PCI/CARDBUS/PCMCIA Bus WLAN MAC
802.11b PCI/CARDBUS/PCMCIA Bus WLAN MAC Controller
Document No.: AX81190-08 / V0.8 / Nov. 15 '03
Features
Single chip multiple bus WLAN MAC Controller
IEEE 802.11b wireless LAN (WLAN) Compatible
Compliant with 802.11b protocol such as DCF,
PCF, WEP, Power management, etc.
Embedded two 8K * 16 bit SRAMs for Tx and Rx
Packet Buffers
Compliant with PCI Bus Standard Ver 2.1(slave
mode)/PCMCIA Bus standard.
Support PCI 16-bit accsee for Registers and 32-bit
accsee for Data
Support both 1/2/5.5/11 Mbps data rate
Support both full-duplex (Test) or half-duplex
operation
Provides an industrial standard interface to
interface with baseband processer and IF/RF chips.
Support 256 bytes EEPROM (used for saving
Configuration Information and address ID)
Support automatic loading of MAC ID and Adapter
Configuration from EEPROM on power-on
initialization
128-pin TQFP low profile package
33/44MHz, 2.5Vcore/3.3V IO operation with 5V
tolerance
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holder.
Product description
The AX81190 is a high performance multiple bus WLAN MAC Controller. The AX81190 contains a 16 bit PCMCIA
interfaces (32-bit PCI/CARDBUS) to host CPU and compliant with PCMCIA Bus Standard Ver 2.2. The AX81190
implements
1Mbps, 2Mbps, 5.5Mbps and 11Mbps WLAN
function based on DSSS (Direct Sequence Spread
Spectrum) of IEEE802.11 /IEEE802.11b WLAN standard. The AX81190 supports an industrial standard(such as Intersil
/RFMD/RaLink) interface for baseband processer and IF/RF chips to simplify the design.
SYSTEM BLOCK DIAGRAM
an, R.O.C.
FA
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
PA
RF
MAC -- AX81190
RaLink 2430 or
BB -- RFMD R3000/3002 or
Intersil 3861/63
IF
PCI/CARDBUS
PCMCIA
ASIX ELECTRONICS CORPORATION
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AX81190 PCI/CARDBUS/PCMCIA Bus WLAN MAC
CONTENTS
1.0 INTRODUCTION
........................................................................................................... 7
1.1 G
ENERAL
D
ESCRIPTION
............................................................................................................ 7
1.2 AX81190 B
LOCK
D
IAGRAM
................................................................................................. 7
1.3 AX81190 P
IN
C
ONNECTION
D
IAGRAM
...................................................................... 8
1.3.1 AX88119 Pin Connection Diagram for PCMCIA Bus Mode
.............................. 8
1.3.2 AX81190 Pin Connection Diagram for PCI/CardBus Mode
.............................. 9
2.0 SIGNAL DESCRIPTION
................................................................................. 10
2.1 PCMCIA B
US
I
NTERFACE
S
IGNALS
G
ROUP
........................................................ 10
2.2 PCI/CARDBUS B
US
I
NTERFACE
S
IGNALS
G
ROUP
....................................... 11
2.3 EEPROM S
IGNALS
G
ROUP
................................................................................................. 12
2.4 S
ERIAL
P
ORT
I
NTERFACE
S
IGNALS
G
ROUP
........................................................... 12
2.5 B
ASEBAND
P
ROCESSER
C
ONTROLLER INTERFACE SIGNALS GROUP
12
2.6 P
OWER
C
ONTROL
I
NTERFACE
S
IGNALS
G
ROUP
................................................ 13
2.7 S
YNTHESIZER CONTROL SIGNAL
I
NTERFACE PINS GROUP
........................ 13
2.8 M
ISCELLANEOUS PINS GROUP
........................................................................................... 13
3.0 REGISTERS OPERATION
......................................................................... 15
3.1 PCI C
ONFIGURATION
R
EGISTER
..................................................................................... 15
3.1.1 Device vendor register -- offset 00h
................................................................................. 15
3.1.2 Command register offset 04h
........................................................................................... 15
3.1.3 Status register offset 06h
.................................................................................................... 15
3.1.4 Revision ID register offset 08h
........................................................................................ 15
3.1.5 Class code register offset 09h
.......................................................................................... 16
3.1.6 Base IO address register offset 10h
............................................................................. 16
3.1.7 Base Memory address register offset 14h
................................................................. 16
3.1.8 CIS pointer offset 28h
........................................................................................................... 16
3.1.9 Subsystem ID 2Ch
................................................................................................................... 16
3.1.10 Interrupt register 3Ch
........................................................................................................ 16
3.2 PCMCIA C
ONFIGURATION
R
EGISTER
....................................................................... 17
3.2.1 COR register 0800h
............................................................................................................... 17
3.2.2 CCR register 0802h
.............................................................................................................. 17
3.2.3 IO base (LSB) 0804h
............................................................................................................. 17
3.2.4 IO base (MSB) 0806h
........................................................................................................... 17
3.3 IO
PORT
................................................................................................................................................. 18
3.3.1 CSR index port
base
............................................................................................... 18
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AX81190 PCI/CARDBUS/PCMCIA Bus WLAN MAC
3.3.2 CSR data port
base + 2
............................................................................................ 18
3.3.3 Tx Data access control port
base + 4
............................................................. 18
3.3.4 Tx data buffer port
base + 6
............................................................................ 18
3.3.5 Rx Data access control port
base + 8
............................................................ 18
3.3.6 Rx data buffer port
base + ah
........................................................................... 18
3.3.7 Soft reset port
base + eh
............................................................................................. 18
3.3.8 Interrupt status port
base + 10h
........................................................................... 18
3.3.9 Interrupt mask port
base + 12h
........................................................................... 19
3.3.10 Rx page status port
base + 14h
....................................................................... 19
3.3.11 Tx page status port1
base + 16h
..................................................................... 19
3.3.12 Tx page status port2
base + 18h
..................................................................... 20
3.3.13 BBP_index port
base + 1ah
............................................................................ 20
3.3.14 BBP_data out port
base + 1ch
......................................................................... 20
3.3.15 BBP_data in port
base + 1eh
............................................................................. 20
3.3.16 Synthesizer control port
base + 20h
............................................................. 20
3.3.17 Synthesizer data port0
base + 22h
................................................................ 20
3.3.18 Synthesizer data port1
base + 24h
................................................................ 20
3.3.19 EE_data port
base + 26h
.................................................................................. 21
3.3.20 EE_cmd/addr port
base + 28h
...................................................................... 21
3.3.21 EE_status_type port
base + 2ah
..................................................................... 21
3.4 MAC C
ONFIGURATION
S
TATUS
R
EGISTERS
........................................................ 22
3.4.1 CSR1 MAC Physical address0 (PADR[15:0])
...................................................... 22
3.4.2 CSR2 MAC Physical address1 (PADR[31:16])
................................................... 22
3.4.3 CSR3 MAC Physical address2 (PADR[47:32])
................................................... 22
3.4.4 CSR4 BSSID Matching Register0, BSSID[15:0]
................................................. 22
3.4.5 CSR5 BSSID Matching Register1, BSSID[31:16]
............................................... 22
3.4.6 CSR6 BSSID Matching Register2, BSSID[47:32]
............................................... 22
3.4.7 CSR7 ~ CSR9 are reserved.
................................................................................................. 22
3.4.10 CSR10 Multicast filter pattern1
................................................................................... 22
3.4.11 CSR11 Multicast filter pattern2
................................................................................... 22
3.4.12 CSR12 Multicast filter pattern3
................................................................................... 22
3.4.13 CSR13 Multicast filter pattern4
................................................................................... 22
3.4.12 CSR14 ~ CSR15 are reserved.
....................................................................................... 23
3.4.16 CSR16 clock pattern
.......................................................................................................... 23
3.4.17 CSR17 Wait md_rdy duration
..................................................................................... 23
3.4.18 CSR18 Short Interframe space timing register ,SIFS
.................................... 23
3.4.19 CSR19 Distributed Interframe space timing register, DIFS/PIFS
........ 23
3.4.20 CSR20 ~ CSR 21 Reserved.
............................................................................................ 23
3.4.22 CSR22 SlotTime Register (SLOT)
............................................................................. 23
3.4.23 CSR23 Backoff timing
........................................................................................................ 23
3.4.24 CSR24 RF3000 modulation duration (Testing)
................................................. 23
3.4.25 CSR25 Power Testing and misc
................................................................................... 23
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AX81190 PCI/CARDBUS/PCMCIA Bus WLAN MAC
3.4.26 CSR26 TXVGC adjust register (support RF3000 only)
................................. 24
3.4.27 CSR27 Tx Beacon/probe response enable register
.......................................... 24
3.4.28 CSR28 TBTT Compensation Register
...................................................................... 24
3.4.29 CSR29 Rx filtering Register
........................................................................................... 24
3.4.30 CSR30 TX Power Ramp-up Control Register1
................................................... 25
3.4.31 CSR31 TX Power Ramp-up Control Register2
................................................... 25
3.4.32 CSR32 TX Power Ramp Control Register3
.......................................................... 25
3.4.33 CSR33 TX Power Ramp Control Register4
.......................................................... 25
3.4.34 CSR34 TX Power Ramp Control Register5
.......................................................... 25
3.4.35 CSR35 BeaconPeriod (BP)
............................................................................................. 25
3.4.36 CSR36 Tx Retry counter
................................................................................................... 25
3.4.37 CSR37 MAC feature register
......................................................................................... 25
3.4.38 CSR38 is Reserved
................................................................................................................... 26
3.4.39 CSR39 Transmit page control register
.................................................................... 26
3.4.40 CSR40 TX Rate control register.
................................................................................. 26
3.4.41 CSR41 response time-out register
.............................................................................. 27
3.4.42 CSR42 RSSI-SQ location register
.............................................................................. 27
3.4.43 CSR43 TSF compensate register
................................................................................. 27
3.4.44 CSR44 Calibration adjust register
............................................................................ 27
3.4.45 CSR45 BBP PLCP Service/Signal field location register ( for Intersil
3861/3863)
................................................................................................................................................... 27
3.4.46 CSR46 BBP PLCP Length field location register (for Intersil
3861/3863)
................................................................................................................................................... 27
3.4.47 CSR47 is Reserved
................................................................................................................... 28
3.4.48 CSR48 Software reset duration
.................................................................................... 28
3.4.49 CSR49 CFP duration register
...................................................................................... 28
3.4.50 CSR50 ATIM duration register
.................................................................................... 28
3.4.51 CSR51 802.11 protocol status
...................................................................................... 28
3.4.52 CSR52 MAC mode status
................................................................................................. 28
3.4.53 CSR53 BBP mode
................................................................................................................. 28
3.4.54 CSR54 SPI chip address
.................................................................................................. 29
3.4.55 CSR55 ~ CSR59 reserved .
................................................................................................. 29
3.4.60 CSR60 CRC32 counter
.......................................................................................................... 29
3.4.61 CSR61 is reserved.
................................................................................................................... 29
3.4.62 CSR62 NAV timer
................................................................................................................. 29
3.4.63 CSR63 TSF timer register0 (TSFR[15:0])
............................................................ 29
3.4.64 CSR64 TSF timer register1 (TSFR[31:16])
......................................................... 29
3.4.65 CSR65 TSF timer register2 (TSFR[47:32])
......................................................... 29
3.4.66 CSR66 TSF timer register3 (TSFR[63:48])
......................................................... 29
3.4.67 CSR67 ~ CSR69 Reserved.
................................................................................................. 29
3.4.70 CSR70 Not my unicast frame counter
...................................................................... 29
3.4.71 CSR71 broadcast and multicast counter
................................................................ 30
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AX81190 PCI/CARDBUS/PCMCIA Bus WLAN MAC
3.4.72 CSR72 RSSI-SQ value
....................................................................................................... 30
3.4.73 CSR73 Outbuf/Inbuf current page pointer
............................................................ 30
3.4.74 CSR74: TX Power Ramp-down Control Register1
.............................................. 30
3.4.75 CSR75: TX Power Ramp-down Control Register2
.............................................. 30
3.4.76 CSR76: TX Power Ramp-down Control Register3
.............................................. 30
3.4.77 CSR77: TX Power Ramp-down Control Register4
.............................................. 30
3.4.78 CSR78: RX_PE de-asserted duration
........................................................................... 30
3.4.79 CSR79: Min size of RX packet
.......................................................................................... 31
3.4.80 CSR80: GPIO status control
............................................................................................. 31
3.4.81 CSR81: GPIO data port
....................................................................................................... 31
3.4.82 CSR82: wep control
................................................................................................................ 31
3.4.83 WEP key matrix (csr83 ~ csr110, 16 bit registers)
.............................................. 31
4.0 PCMCIA DEVICE ACCESS FUNCTIONS
................... 32
4.1 A
TTRIBUTE
M
EMORY ACCESS FUNCTIONS
.
........................................................... 32
4.2 I/O
ACCESS FUNCTIONS
.
......................................................................................................... 32
5.0 ELECTRICAL SPECIFICATION AND
TIMINGS
................................................................................................................................................. 33
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
..................................................................................... 33
5.2 G
ENERAL
O
PERATION
C
ONDITIONS
............................................................................. 33
5.3 DC C
HARACTERISTICS
............................................................................................................ 33
5.4 A.C. T
IMING
C
HARACTERISTICS
..................................................................................... 34
5.4.1 CLOCK
.............................................................................................................................................. 34
5.4.2 PCMCIA Reset Timing
............................................................................................................. 34
5.4.3 PCMCIA Attribute Memory Read Timing
.................................................................... 35
5.4.4 PCMCIA Attribute Memory Write Timing
................................................................... 36
5.4.5 PCMCIA I/O Read Timing
..................................................................................................... 37
5.4.6 PCMCIA I/O Write Timing
.................................................................................................... 38
5.4.7 Synthesizer Timings
................................................................................................................... 39
5.4.8 Serial Port Timings
.................................................................................................................... 40
5.4.9 TX Path Waveforms
................................................................................................................... 41
5.4.10 RX Path Waveforms
................................................................................................................ 42
6.0 PACKAGE INFORMATION
.................................................................... 43
APPENDIX A: APPLICATION NOTE 1
....................................... 44
A.1 E
XTERNAL
EEPROM
FORMAT
....................................................................................... 44
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