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Электронный компонент: AX88873

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ASIX ELECTRONICS CORPORATION
Doc. No. AX873-11.DOC Date : APR/26/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88873P
10/100BASE Dual Speed Repeater Controller
10/100BASE Dual Speed 8-Port Repeater
Ver. 1.1
Features
IEEE 802.3u repeater compatible
Supports 8 10/100Mbps RMII I/F repeater ports
Accompany with AX88872 to build a low cost dual
speed repeater solution
Up-to 4 repeaters can be cascaded for vertical
expansion
Up-to 3 chips can be cascaded locally for horizontal
expansion
All ports can be separately isolated or partitioned in
response to fault condition
Separate jabber and partition state machines for
each port
Per-port LED display for Jabber, Partition, Activity
and global collision, utilization (%) for
10/100Mbps presentation
Power on LED diagnosis. All the LED display will
follow the "ON-OFF-ON-OFF-Normal" operation
procedure during/after power on reset
50MHz Operation, 3.3volt and 128-pin PQFP
Product description
The AX88873 10/100Mbps Dual Speed repeater Controller is a counterpart of AX88872 without built in 4-ports
switch. It is design for low cost dual speed dumb HUB application.
The AX88873 directly supports up-to eight 10/100Mbps automatic links RMII interfaces. Maximum up-to 96
repeater ports can be constructed by stacking 1 AX88872 and 2 AX88873 chips horizontally and then cascading 4
horizontal boards vertically.
With using 128-pin low cost package, accompany with AX88872 to build up low cost dual speed repeater application.
Not only perform the repeater function but gain additional 2 switch ports. The 2 dual speed switch ports are connected
to external MII or RMII interfaces PHY for various applications. For example, one port is use for down link and the
other is used for up link to extend the network topology. The other case is one port for up link and the other port for
server.
The AX88873 is designed base on IEEE 802.3u clause 27 " Repeater for 100Mb/s base-band networks" It is fully
compatible with IEEE 802.3u standard. Please refer Ax872-11.doc to get more information about AX88872.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
AX88873 #1
Repeater Controller
Buffer
100Mbps horizontal cascade
10Mbps and 100Mbps Vertical cascade upto 4 stacks
AX88873 #0
Repeater Controller
AX88872 #0
Swipeater Controller
10Mbps horizontal cascade
2 Quad RMII PHY
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Up-link
PHY for Down-link or Server
ASIX ELECTRONICS CORPORATION
2
CONFIDENTIAL
AX88873P 10/100Mb Repeater Controller PRELIMINARY
CONTENTS
1.0 AX88873 OVERVIEW ....................................................................................................................................... 4
1.1 G
ENERAL
D
ESCRIPTION
...................................................................................................................................... 4
1.2 AX88873 B
LOCK
D
IAGRAM
: .............................................................................................................................. 4
1.3 P
IN
C
ONNECTION
D
IAGRAM
............................................................................................................................... 5
2.0 PIN DESCRIPTION ........................................................................................................................................... 6
2.1 RMII
INTERFACE FOR REPEATER PORTS
............................................................................................................... 6
2.1.1 Repeater Port 0.......................................................................................................................................... 6
2.1.2 Repeater Port 1.......................................................................................................................................... 6
2.1.3 Repeater Port 2.......................................................................................................................................... 7
2.1.4 Repeater Port 3.......................................................................................................................................... 7
2.1.5 Repeater Port 4.......................................................................................................................................... 7
2.1.6 Repeater Port 5.......................................................................................................................................... 7
2.1.7 Repeater Port 6.......................................................................................................................................... 8
2.1.8 Repeater Port 7.......................................................................................................................................... 8
2.2 E
XPANSION
B
US
I
NTERFACE FOR
100 M
BPS
......................................................................................................... 8
2.3 E
XPANSION
B
US
I
NTERFACE FOR
10 M
BPS
........................................................................................................... 9
2.4 LED D
ISPLAY
.................................................................................................................................................. 10
2.5 M
ISCELLANEOUS
.............................................................................................................................................. 10
2.6 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 11
3.0 FUNCTIONAL DESCRIPTION ..................................................................................................................... 12
3.1 R
EPEATER
S
TATE
M
ACHINE
.............................................................................................................................. 12
3.2 RXE /TXE C
ONTROL
...................................................................................................................................... 12
3.3 J
ABBER
S
TATE
M
ACHINE
.................................................................................................................................. 12
3.4 P
ARTITION
S
TATE
M
ACHINE
............................................................................................................................. 12
3.5 LED D
ISPLAY
I
NTERFACE
................................................................................................................................ 13
4.0 INTERNAL REGISTERS ................................................................................................................................ 14
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 15
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 15
5.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 15
5.3 DC C
HARACTERISTICS
..................................................................................................................................... 15
5.4 AC
SPECIFICATIONS
......................................................................................................................................... 16
5.4.1 RMII Interface Timing TX & RX............................................................................................................... 16
5.4.2 MII Interface Timing TX & RX ................................................................................................................. 17
5.4.3 LED DISPLAY ......................................................................................................................................... 18
5.4.4 LED Display after Reset........................................................................................................................... 18
6.0 PACKAGE INFORMATION........................................................................................................................... 19
APPENDIX A: APPLICATIONS.......................................................................................................................... 20
A.1 16-
PORT
(24-
PORT
)
REPEATER WITH
2-
PORT SWITCH
......................................................................................... 20
A.2 16-
PORT REPEATER WITH UPTO
4
STACKS
......................................................................................................... 20
A.3 16-
PORT REPEATER WITH UPTO
4
STACKS UP
-
LINK TO EXTERNAL SWITCH
........................................................... 21
ASIX ELECTRONICS CORPORATION
3
CONFIDENTIAL
AX88873P 10/100Mb Repeater Controller PRELIMINARY
FIGURES
F
IG
- 1 AX88873 B
LOCK
D
IAGRAM
............................................................................................................................. 4
F
IG
- 2 P
IN
C
ONNECTION
D
IAGRAM
.............................................................................................................................. 5
F
IG
- 3 A
PPLICATION FOR
LED
DISPLAY
..................................................................................................................... 13
ASIX ELECTRONICS CORPORATION
4
CONFIDENTIAL
AX88873P 10/100Mb Repeater Controller PRELIMINARY
1.0 AX88873 Overview
1.1 General Description
The AX88873 is a simple dual speed repeater that provides two expansion buses for 10M and 100M
segments respectively. Accompany with AX88872 (build-in a 4-port switch) can construct high port
count (16 ports or 24 ports) application and gain 2 additional switch ports. Additional two switch
ports are also useful for up-link or connection of server.
The pin count of chip is reduced to 128 when design uses RMII I/F instead of MII. It is not only
simplify the design but also user can choose low cost RMII Quad PHY.
1.2 AX88873 Block Diagram:
10/100
Q-PHY
10/100
Q-PHY
RMII
I/F
RMII /MII
translation
for Repeater
Port 0 -7
Repeater State
Machine of 100Mbps
Led Interface
Cascade
Arbitration Logic
of 100Mbps
Repeater State
Machine of 10Mbps
Cascade
Arbitration Logic
of 10Mbps
Per Port Jabber
Detection
Per Port Partition
Detection
Fig - 1 AX88873 Block Diagram
ASIX ELECTRONICS CORPORATION
5
CONFIDENTIAL
AX88873P 10/100Mb Repeater Controller PRELIMINARY
1.3 Pin Connection Diagram
Fig - 2 Pin Connection Diagram
VDD
VSS
LED_CK
VSS
VSS
LED<1>
LED<0>
VSS
VSS
TXD1[0]
TXD1[1]
CRS_DV2
RXD2[0]
TXEN2
TXD2[0]
RXD2[1]
TXD2[1]
TXD5[1]
RXD5[1]
TXD5[0]
TXEN5
CRS_DV5
RXD5[0]
CRS_DV6
RXD6[1]
RXD6[0]
TXD6[0] TXD6[1]
TXEN6
CRS_DV7
RXD7[1]
RXD7[0]
TXD7[0]
TXEN7
TXD7[1]
TIRD[1]
TIRD_CK
/TIRD_V
TIRD[0]
TIRD_ODIR
MDO
MDC
NC
NC
VDD
DAISY_IN
DAISY_OUT
NC
/RST
/TEST
VDD
VSS
VDD
REF_CLK
SPEED2
SPEED5
SPEED6
SPEED7
123
118
122
78
70
64
54
41
32
24
12
8
117
75
57
42
26
31
21
107
105
66 65
63
60
25
16
13
3
7
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
68
58
56
55
45
23
53
116
113
59
36
34
1
124
108
28
22
9
126
119
110
121
79
74
80
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
40
37
50
18
14
AX88873
103
104
82
91
81
86
93
94
84
87
95
96
90
88
92
85
89
83
98 97
99
100
102
101
VSS SPEED4
RXD4[1]
TXEN4 TXD4[0] TXD4[1]
RXD4[0]
CRS_DV4
TXD3[1]
TXD3[0]
TXEN3
RXD3[1]
CRS_DV3 RXD3[0]
VDD
SPEED3
/LTIR_ACT[0]
/LTIR_ACT[1]
/LTIR_ACT[2]
/LHIR_ACT[0]
/LHIR_ACT[1]
/LHIR_ACT[2]
VSS
/HIR_ACTI[0]
/HIR_ACTI[1]
/HIR_ACTI[2]
/HIR_ACTI[3]
/TIR_ACTI[0]
/TIR_ACTI[1]
/TIR_ACTI[2]
/TIR_ACTI[3]
/TIR_ACTO[0]
/TIR_ACTO[1]
/TIR_ACTO[2]
/TIR_ACTO[3]
TIRD[2]
TIRD[3]
VDD
/HIR_ACTO[0]
/HIR_ACTO[1]
/HIR_ACTO[2]
/HIR_ACTO[3]
VSS
VSS
VDD
HIRD[0] /HIRD_V
HIRD[2]
HIRD_CK
HIRD[3]
HIRD[1]
HIRD_ODIR
NC
VSS
NC
VSS
SPEED1
RXD1[1]
RXD1[0]
CRS_DV1
TXEN1
CRS_DV0
RXD0[1]
RXD0[0]
TXD0[1]
TXD0[0]
TXEN0
VDD
VSS
SPEED0